Study on Neutron Damage Dynamics of Semiconductor Crystal

用来自氚加速器的聚变中子辐照硅表面势垒探测器(Si-SBD)。探测器的泄漏电流随着中子注量的增加而成比例增加，这决定了Si-SBD的中子损伤常数。由DT和DD中子损伤常数的比值确定了DT和DD中子损伤的相关系数为2.3。利用离子输运程序TRIM-90和Si-SBD的中子反应数据，计算了DT和DD中子位移损伤率。计算得到的DT和DD中子损伤的相关系数与Si-SBD辐照实验的结果一致。为了检验中子在存储IC上引起的软误差，用14 MeV的中子辐照了几种1Mbit的CMOSRAM集成电路。考虑芯片中的单元数目，我们得到了1Mbit芯片的6-9×10^-14&gt；cm^2的中子磁化率常数，即比特软恐怖截面。这意味着软错误是由存储单元中有限区域内的中子反应引起的。BIT软误差截面值与基于TRIM-90程序和ENDF/B-VI中子截面数据的蒙特卡罗程序计算机模拟计算的结果基本一致。

A silicon surface barrier detector (Si-SBD) was irradiated with fusion neutrons from a deuteron accelerator. The leakage current of the detector increased proportionally with neutron fluence, which determined the neutron damage constant for the Si-SBD.The correlation factor of the DT and DD neutron damage in the Si-SBD was determined from the ratio of the DT and DD neutron damage constants and was found to be 2.3. We also calculated the rate of DT and DD neutron displacement damage for Si by using the ion transport code TRIM-90 and data on neutron reactions in the Si-SBD.The correlation factor of DT and DD neutron damage from the calculation agreed with that from the Si-SBD irradiation experiment.In order to examine the neutron induced soft-error on memory ICs, several kinds of 1 Mbit CMOS SRAM ICs were irradiated with 14 MeV neutrons. Considering the cell population in the chip, we obtained the neutron susceptibility constant, i.e. bit softerror cross section of 6-9*10^<-14> cm^2 for 1 Mbit CMOS SRAM ICs. This means that a soft-error is caused by neutron reactions in a limited region in a memory cell. The bit soft-error cross section value agreed roughly with that calculated by computer simulation with a Monte Carlo program based on the TRIM-90 code and the ENDF/B-VI neutron cross section data.