Study on Fusion-neutron Damage Dynamics of Semiconductor Materials

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In order to examine the fusion neutron induced soft-error on memory ICs, several kinds of 1 Mbit CMOS SRAM ICs were irradiated with 14 MeV neutrons. Considering the cell population in the chip, we obtained the neutron susceptibility constant, i.e.bit soft-error cross section of 6-9*10^<-14> cm^2 for 1 Mbit CMOS SRAMs. This means that a soft-error is caused by neutron reactions in a limited region in a memory cell. The bit soft-error cross section value agreed roughly with that calculated by computer simulation with a Monte Carlo program based on the ion transport code TRIM-90 and the ENDF-B-VI neutron cross section data. Also we developed a special ion-beam apparatus for the examination of the soft-error mechanism.A silicon surface barrier detector (Si-SSD) was irradiated with neutrons from a deuteron accelerator. The leakage current increased proportionally with neutron fluence, which determined the neutron damage constant for the Si-SSD.The correlation factor of the DT and DD neutron damage in the Si-SSD was determined from the ratio of the DT and DD neutron damage constant and was found to be 2.3. We also calculated the rate of DT and DD neutron displacement damage for Si by using the TRIM-90 code and data on neutron reactions in the Si-SSD.The correlation factor of DT and DD neutron damage from the calculation agreed with that from the Si-SSD irradiation experiment.