Study on LSI testing for multiple fault models

随着LSI设计和制造技术的进步，出现了新的问题，例如不完整/非法连接、影响时序行为的延迟故障或串扰噪声。为了检测几种类型的故障描述为不同的模型，本研究的目的是提高固定故障的测试模式的缺陷覆盖率，高质量的测试生成延迟故障，故障诊断，以及这些主题的基础技术。（1）提高固定型故障测试模式桥接故障覆盖率的研究结果：通过识别固定型故障测试模式中的无关位，提出了一种将逻辑值重新分配给无关位的方法，有效地提高了桥接故障覆盖率。(2)研究了更精确的测试松弛方法。结果：我们提出了一种新的测试松弛方法，该方法可以识别出比以往方法更多的无关位。作为该方法的一个应用，我们提出了一种降低全扫描电路测试成本的方法。(3)结果：分别针对过渡延迟故障和路径延迟故障提出了一种测试生成方法，使得测试集规模较小，可以检测到大量的故障。(4)基于X-故障模型的故障诊断方法研究结果：提出了一种基于X-故障模型的故障诊断方法。(5)结果：将编译逻辑仿真技术与事件驱动仿真技术相结合，开发了逻辑电路快速故障仿真器。

With the progress of design and manufacturing technology for LSIs, new problems occur such as incomplete/illegal connections, delay faults that affect timing behavior, or crosstalk noise. In order to detect several types of faults described as various models, this research aims at enhancing defect coverage of test patterns for stuck-at faults, high quality test generation for delay faults, fault diagnosis, and fundamental techniques for these subjects. More specifically, we worked on the following five themes, and obtained results as follows :(1) Research on improvement bridging fault coverage of test patterns for stuck-at faults.Results : By identifying don't care bits in given test patterns for stuck-at faults, we developed a method to reassign logic values to the don't care bits so as to increase bridging fault coverage efficiently.(2) Research on more precise test relaxationResults : We developed a method that can identify more don't care bits than other methods published before. As an application of the developed method, we proposed a method of test cost reduction for full scan circuits.(3) Research on high quality test for delay faultsResults : We developed a test generation method for transition delay faults and path delay faults respectively such that a test set with small size detects many faults.(4) Research on fault diagnosis using X-fault modelResults : We developed a per-test fault diagnosis method using X-fault model that implies various fault models.(5) Research on accelerating fault simulation techniquesResults : By combining a compiled logic simulation technique with an event-driven simulation technique, we developed fast fault simulator for logic circuits.