Understanding of carrier transport mechanism in Ge MOS interfaces and establishment of mobility enhancement technologies

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We have clarified from comparison between effective and Hall mobility of Ge MOSFETs that inversion-layer carriers are trapped into interface states locating inside the conduction and valence bands, leading to the reduction in the effective mobility. Also, atomic deuterium annealing is fond to reduce the interface states and to increase the effective mobility. Also, HfO2/Al2O3/GeOx/Ge MOSFETs with EOT of 0.76 nm, realized by ECR plasma oxidation, exhibited peak electron and hole mobility of 690 and 550 cm2/Vs, respectively. The surface orientation dependence of the effective mobility has also been revealed. In addition, we demonstrated GOI n- and p-MOSFETs with GOI thinner than 20 nm, fabricated by the Ge condensation and Ge wafer bonding, and evaluated the mobility behaviors.