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Understanding of carrier transport mechanism in Ge MOS interfaces and establishment of mobility enhancement technologies

Understanding of carrier transport mechanism in Ge MOS interfaces and establishment of mobility enhancement technologies
Ge MOS界面载流子传输机制的理解及迁移率增强技术的建立
批准号:
23246058
负责人:
TAKAGI Shinichi
金额:
$31.45万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (A)
财政年份:
2011
资助国家:
日本
项目状态:
已结题
起止时间:
2011-04-01 至 2014-03-31

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中文摘要
翻译
通过对Ge MOSFET有效迁移率和霍尔迁移率的比较,我们阐明了反型层载流子被捕获到位于导带和价带内的界面态,导致了有效迁移率的降低。此外,氢原子的退火有利于降低界面态,提高有效迁移率。ECR等离子体氧化制备的EOT为0.76 nm的HfO2/Al_2O_3/Geox/Ge MOSFET的电子迁移率和空穴迁移率峰值分别为690和550 cm~2/V。还揭示了有效迁移率与表面取向的关系。此外,我们还展示了用Ge凝聚和Ge晶片键合方法制备的GOI小于20 nm的n-MOSFET和p-MOSFET,并对其迁移率进行了评价。
英文摘要
We have clarified from comparison between effective and Hall mobility of Ge MOSFETs that inversion-layer carriers are trapped into interface states locating inside the conduction and valence bands, leading to the reduction in the effective mobility. Also, atomic deuterium annealing is fond to reduce the interface states and to increase the effective mobility. Also, HfO2/Al2O3/GeOx/Ge MOSFETs with EOT of 0.76 nm, realized by ECR plasma oxidation, exhibited peak electron and hole mobility of 690 and 550 cm2/Vs, respectively. The surface orientation dependence of the effective mobility has also been revealed. In addition, we demonstrated GOI n- and p-MOSFETs with GOI thinner than 20 nm, fabricated by the Ge condensation and Ge wafer bonding, and evaluated the mobility behaviors.
期刊论文(106)
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会议论文
III-V/Ge integration on Si platform for electronic-photonic integrated circuits
用于电子光子集成电路的 Si 平台上的 III-V/Ge 集成
DOI: --
发表时间: 2012
期刊:
影响因子: --
作者: [Xinqiang WANG, et al., M. Takenaka]
通讯作者: M. Takenaka
Improvement of High Ns Mobility of Ge MOSFETs by Reducing GeOx/Ge Interface Roughness
通过降低 GeOx/Ge 界面粗糙度提高 Ge MOSFET 的高 Ns 迁移率
DOI: --
发表时间: 2013
期刊:
影响因子: --
作者: [X.Wang, A.Rahim Ruslinda, H.Kawarada, R. Zhang]
通讯作者: R. Zhang
Prospective and critical issues of III-V/Ge CMOS on Si platform
Si平台上III-V/Ge CMOS的前景和关键问题
DOI: 10.1149/1.3569921
发表时间: 2011
期刊: ECS Trans.
影响因子: --
作者: [Tetsuya Uchimoto, Toshiyuki Takagi, Xiaodong Deng, Thomas Monnier, Joel Courbon, Thierry Douillard, Varlot Mansenelli, S.Takagi and M.Takenaka]
通讯作者: S.Takagi and M.Takenaka
III-V/Ge CMOS Device Technologies for Future Logic LSIs
用于未来逻辑 LSI 的 III-V/Ge CMOS 器件技术
DOI: --
发表时间: 2014
期刊:
影响因子: --
作者: [Shohei Ueno, Takashi Todaka, Masato Enokizono, J.Ohta, S.Takagi and M.Takenaka]
通讯作者: S.Takagi and M.Takenaka
81
    Understanding of mechanisms dominating inversion-layer mobility in strained-Si MOSFETs and establishment of guideline for the mobility enhancement
    • 批准号:
      20246055
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $23.21万
    • 财政年份:
      2008
    • 负责人:
      TAKAGI Shinichi
    • 依托单位:
    Nano-structure functional devices based Ge-based channels
    • 批准号:
      18063005
    • 项目类别:
      Grant-in-Aid for Scientific Research on Priority Areas
    • 资助金额:
      $69.38万
    • 财政年份:
      2006
    • 负责人:
      TAKAGI Shinichi
    • 依托单位:
    Study on physical models for understanding the properties of strained-Si MOS Transistors
    • 批准号:
      16206029
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $30.78万
    • 财政年份:
      2004
    • 负责人:
      TAKAGI Shinichi
    • 依托单位:
    海外基金