A New Functional MOS Transistor Featuring Neuron Functions
A New Functional MOS Transistor Featuring Neuron Functions
批准号:
02402032
负责人:
SHIBATA Tadashi
金额:
$8.64万
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (A)
财政年份:
1990
资助国家:
日本
项目状态:
已结题
起止时间:
1990 至 1991
中文摘要
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英文摘要
A new functional MOS transistor has been developed which works more intelligently than a mere switching device. The functional transistor calculates weighted sum of all input signals at the gate level, and controls the "on" and "off" of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET or neuMOS (nuMOS) in short. The device is composed of a floating gate and plural of input gates that are capacitively interacting with the floating gate. As the gate-level sum operation is perfomied in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFET's as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit a … More pplications have been explored. neuMOS inverters and neuron circuits, variable threshold transistors and inverters, linear resistors, and neuMOS source follower circuits and single gate D/A converters are described. The concept of a Soft Hardware Logic Circuit implemented by neuMOS transistors has been also developed. The circuit exhibits a very interesting feature that the logical function of the circuit is arbitrarily altered by external signals without any changes in the hardware configuration. When fixed function logic circuits are implemented by nuMOS transistors, the number of transistors as well as of interconnections can be dramatically reduced as compared to their conventional CMOS-design counterparts. 4-bit flash A/D converter, for instance, can be constructed by only 28 transistors although 398 transistors are required in conventional design. Basic operations of these circuits have been experinientally verified by fabricating test circuits using double polysilicon CMOS process. Less
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T,Shibata: "An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations" Technical Digest,International Electron Devicas Meeting 1991,Washington D.C.919-922 (1991)
T,Shibata:“具有门级加权和和阈值操作的智能 MOS 晶体管”技术文摘,1991 年国际电子设备会议,华盛顿特区 919-922 (1991)
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T. Shibata and T. Ohmi: "A new-concept transistor realizing neuron functions by a single device" Nikkei Microdevices. 79. (1992)
T. Shibata 和 T. Ohmi:“通过单个器件实现神经元功能的新概念晶体管”Nikkei Microdevices。
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T. Shibata and T. Ohmi: "An intelligent MOS transistor featuring gate-level weighted-sum and threshold operations" Technical Digest, International Electron Devices Meeting 1991, Washington D. C.919-922 (1991)
T. Shibata 和 T. Ohmi:“具有门级加权和和阈值操作的智能 MOS 晶体管”技术文摘,1991 年国际电子器件会议,华盛顿特区 C.919-922 (1991)
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T.Shibata: "An Intelligent MOS Transistor Featuring GateーLevel Weighted Sum and Threshold Operations" Technical Digest,International Electron Devices Meeting 1991,Washington D.C. 919-922 (1991)
T. Shibata:“具有门级加权和和阈值操作的智能 MOS 晶体管”技术文摘,1991 年国际电子器件会议,华盛顿特区 919-922 (1991)
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T.Shibata: "A New Logic Circuit Design Using Neuron MOSFET'S" IEEE SolidーState Circuits.
T. Shibata:“使用神经元 MOSFET 的新逻辑电路设计”IEEE 固态电路。
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