A NEURON-MOS NEURAL NETWORK FEATURING ON-CHIP SELF-LEARNING CAPABILITY

点击翻译按钮获取中文摘要

Neural network hardware having an on-chip self-learning capability has been developed using a high-functionality device called Neuron MOS Transistor (vMOS) as a key circuit element. A vMOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based the charge sharing among multiple capacitors. An electronic synapse cell been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept vMOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V_<DD> power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making in fully compatible to the on-chip self-learning architecture of vMOS neural networks. A new hardware-oriented learning algorithm called Hardware Backpropagation (HBP) has been developed by simplifyng and modifying the original Backpropagation (BP) algorithm. As a result, all learning actions are controlled by only digital signals with simple on-chip digital circuitry, thus enabling the direct implementation of the learning algorithm on the chip. The analog nature of the learning control is created by vMOS circuit technology. A new concept of "learning enhancement" has been introduced in order to guarantee the long-term stability of the learned state of analog neural networks. After optimization of the circuit parameters by extensive computer simulation, it has been demonstrated that HBP is superior to original BP both in the learning performance and in the generalization capability. The basic operation of the vMOS neural network having all above features has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process.