A NEURON-MOS NEURAL NETWORK FEATURING ON-CHIP SELF-LEARNING CAPABILITY

具有片上自学习功能的 NEURON-MOS 神经网络

• 批准号: 05505003
• 负责人: SHIBATA Tadashi
• 金额: $ 21.06万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research (A)
• 财政年份: 1993
• 资助国家: 日本
• 起止时间: 1993 至 1994
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-05505003/
• 关键词: NEURAL NETWORK; SELF LEARNING; HARDWARE LEARNING; NEURON MOS TRANSISTOR; SYNAPSE; EEPROM; BACK PROPAGATION; GENERALIZATION; 学習アルゴリズム; ヘブルール; 自己学習; アナログニューラルネットワーク; フローティングゲート; ハードウェア学習アルゴリズム

Neural network hardware having an on-chip self-learning capability has been developed using a high-functionality device called Neuron MOS Transistor (vMOS) as a key circuit element. A vMOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based the charge sharing among multiple capacitors. An electronic synapse cell been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept vMOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V_<DD> power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making in fully compatible to the on-chip self-learning architecture of vMOS neural networks. A new hardware-oriented learning algorithm called Hardware Backpropagation (HBP) has been developed by simplifyng and modifying the original Backpropagation (BP) algorithm. As a result, all learning actions are controlled by only digital signals with simple on-chip digital circuitry, thus enabling the direct implementation of the learning algorithm on the chip. The analog nature of the learning control is created by vMOS circuit technology. A new concept of "learning enhancement" has been introduced in order to guarantee the long-term stability of the learned state of analog neural networks. After optimization of the circuit parameters by extensive computer simulation, it has been demonstrated that HBP is superior to original BP both in the learning performance and in the generalization capability. The basic operation of the vMOS neural network having all above features has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process.

具有片上自学习能力的神经网络硬件采用了一种高功能的神经元MOS晶体管（vMOS）作为关键电路元件。基于多个电容之间的电荷共享，vMOS可以在单个晶体管水平上对多个输入信号进行加权求和和阈值处理。将一个浮栅EEPROM存储单元合并到一个新概念的vMOS差分源-跟随电路中，构建了一个由6个晶体管组成的电子突触单元。在单个V_<DD>电源下，突触可以同时表示正（兴奋）权和负（抑制）权，并且不受待机功耗的影响。通过在每个细胞电路中采用简单的自反馈机制，突触记忆的权重更新特性具有良好的线性，从而使其与vMOS神经网络的片上自学习架构完全兼容。通过对原有的反向传播算法进行简化和改进，提出了一种新的面向硬件的学习算法——硬件反向传播算法（HBP）。因此，所有的学习动作都是由数字信号控制，采用简单的片上数字电路，从而可以直接在芯片上实现学习算法。学习控制的模拟性质是由vMOS电路技术创造的。为了保证模拟神经网络学习状态的长期稳定性，引入了“学习增强”的新概念。通过大量的计算机仿真对电路参数进行优化，证明了HBP在学习性能和泛化能力上都优于原始BP。利用双多晶硅CMOS工艺制作的测试电路，实验验证了具有上述所有特征的vMOS神经网络的基本操作。

项目成果

T.Shibata: "Implementing Intelligence on Silicon using Neuron-like functional MOS transistors" Proc.7th Conference on Neural Information Processing Systems : Natural and Synthetic,(NIPS'93). (1994)

T.Shibata：“使用类似神经元的功能 MOS 晶体管在硅上实现智能”Proc.7th 神经信息处理系统会议：自然与合成，(NIPS93)。

T.Ohmi: "The concept of bour-terminal-device and its significance in the implementation of intelligent electronic circuits" IEICE Transactions in Electronics. (1994)

T.Ohmi：“bour-terminal-device 的概念及其在智能电子电路实现中的意义”IEICE Transactions in Electronics。

Hideo Kosaka, Tadashi Shibata, Hiroshi Ishii, and Tadahiro Ohmi: "An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning neuron-MOS neural networks" IEEE Trans.Electron Devices. Vol.42、No.1. 135-143 (1995)

Hideo Kosaka、Tadashi Shibata、Hiroshi Ishii 和 Tadahiro Ohmi：“用于自学习神经元 MOS 神经网络的出色的权重更新线性 EEPROM 突触存储单元”IEEE Trans.Electron Devices 第 42 卷，第 135 期。 -143 (1995)

H.Ishii: "Hardware-learning neural netwark LSI using a highly functional transistor simulating neuron actions" Proc.International Joint Conference on Neural Networks'93,Nagoya. 907-910 (1993)

H.Ishii：“使用高功能晶体管模拟神经元动作的硬件学习神经网络 LSI”Proc.International Joint Conference on Neural Networks93，名古屋。

T.Shibata: "Hardware Implementation of Intelligence on silicon using four-terminal devices" Proc.International Conference an Advanced Microelectronic Deviees and Processing. 743-750 (1994)

T.Shibata：“使用四端设备在硅上实现智能的硬件”Proc.国际先进微电子设备和处理会议。