Study on Ultra High-bandwidth Interconnect Circuits for System-on-a-chip

随着CMOS工艺技术的不断进步和芯片面积的不断扩大，目前CMOS大规模集成电路设计中出现了许多严重的问题，如工艺偏差、器件缺陷、设计和测试成本等。为了避免这些问题，使用功能宏块的2维结构被认为是未来LSI配置的有希望的候选者。然而，这种结构的关键是如何实现这些宏之间的高带宽互连。本研究结合高速类比电路设计技术与大规模记忆体设计技术，发展出一种新颖的内连线技术，其结果为：1）发展出一种新颖的高频宽四电压位准内连线电路。它包括工艺变化检测器，以稳定输出电压电平。2)测试芯片也通过VDEC开发，以证明这种新电路的实用性。测量结果证实了4伏运行。3）开发了一个基于图像处理的非易失性存储器工艺偏差定量分析系统。

According to the shrink of CMOS process technology and enlargement of the chip area, there are many serious problems in recent CMOS LSI design; such as process variations, device defects, costs for design and test. In order to avoid these problems, 2-demensional structure using functional macro blocks is considered as a promising candidate of a future LSI configuration. However the key in this structure is how to realize the high-bandwidth interconnections among these macros. In this study, both High-speed analog circuit design technology and large-scale memory design technology are employed to develop the novel interconnect technology.As a result, 1)new high-bandwidth interconnect circuits which uses 4-voltage-level was developed. It includes process variation detector to stabilize the output voltage level. 2)The test chip was also developed via VDEC to demonstrate the usefulness of this new circuit. The 4-volatege-level operation was confirmed by the measured results. 3)A quantitive analysis system using image processing for non-volatile memories was also developed to evaluate process variation.