Device Process for Integrated Systems Composed of Dislocation-Free III-V-N Alloys and Silicon

为了在单个芯片上实现新型的光电集成系统，将光学器件和电子电路结合在一起，已经开发出了基本的工艺技术。这些技术是基于Si和III-V-N合金的无位错异质外延。我们研究了III-V-N合金中N原子产生的点缺陷及其相关的光学和电学性质。通过快速热退火和抑制射频等离子体源中产生的N离子的辐照，减少了缺陷。这些效应导致了光致发光强度的增加和Ga间隙的减少。此外，还成功地生长了具有直接跃迁的InGaPN层。结果表明，缺陷是电子导电性差的原因。N型和P型电子电导分别由S和镁掺杂控制，Si和III-V-N合金是互杂质。应用本项目研制的双室分子束外延系统，抑制了外延过程中的污染。对硅MOS FET和III-V-N合金发光二极管(LED)的工艺条件进行了优化。通过降低栅氧化层生长温度，抑制了Si和III-V-N合金层之间的相互扩散。结果表明，采用与MOS集成电路相同的工艺流程，可以制备出新型的光电集成系统。在硅衬底上生长了Si/III-V-N合金双异质结复合层。首次应用该工艺流程在最上层的硅层和III-V-N合金的DH层分别制作了用于集成系统的基本器件MOS FET和LED。LED的光输出由MOS FET控制。这些结果意味着为超并行网络等新型集成系统开发了基本的器件工艺技术。

Basic process technologies have been developed for realizing novel optoelectronic integrated systems in a single chip, in which optical devices and electronic circuits were combined. These technologies were based on the dislocation-free heteroepitaxy of Si and III-V-N alloys.We have investigated point defects originated in N atoms in the III-V-N alloys and optical and electronic properties related to the defects. The defects were decreased by rapid thermal annealing and by suppressing the irradiation of N ions generated in an rf-plasma source. The effects led to the increase in photoluminescence intensity and the reduction of Ga interstitials. In addition, InGaPN layers with direct transition were successfully grown. It was clarified that the defects cause poor electronic conductivity. N-and p-type electronic conductivities were controlled by S and Mg doping, respectively.Si and III-V-N alloys were mutually impurities. Contamination during epitaxy was suppressed by applying a two-chamber molecular beam epitaxy system which was developed in this project. Process conditions for both devices of a Si MOS FET and a III-V-N alloy light emitting diode (LED) were optimized. Mutual diffusion between the Si and III-V-N alloy layers was suppressed by decreasing the growth temperature of a gate oxide. As a result, it became apparent that the novel optoelectronic integrated systems could be fabricated by applying a process flow followed to that of MOS integrated circuits.The composite layer of Si/III-V-N alloy double heterostructure (DH) layers was grown on a Si substrate. Elemental devices for the integrated systems, MOS FETs and LEDs, were fabricated in the topmost Si layer and the III-V-N alloy DH layer, respectively by applying the process flow for the first time. The optical output of the LED was controlled by the MOS FET. These results mean that the basic device process technologies were developed for the novel integrated systems such as ultra-parallel networks and others.