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High-Performance Parallel Simulation Technology for Advanced Information System Development

先进信息系统开发的高性能并行仿真技术

基本信息

批准号：
17300015
负责人：
NAKASHIMA Hiroshi
金额：
$ 9.63万
依托单位：
Kyoto University (2006-2007)Toyohashi University of Technology (2005)
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2005
资助国家：
日本
起止时间：
2005 至 2007
项目状态：
已结题

项目摘要

The research has been pursued aiming at the parallelization and performance improvement of cycle accurate simulation (CAS) for advanced IT systems with microprocessors as their key components. The major achievements of the research are the following simulation techniques.1. Our parallelized CAS is combined with an in-order execution simulator to produce approximated partial results of the parallel simulation. In order to avoid that this sequential in-order simulator became a bottleneck, we devised an acceleration technique to generate a simulator specific to each workload automatically. This technique achieves up to 34-fold performance improvement for instruction level simulation.2. We devised a new parallel simulation method in which the process of a simulation is divided into intervals along with time axis so that the intervals me executed in parallel The problem arisen from the dependency between intervals is solved by speculatively executing each interval with approximated partial result of preceding intervals using in-order simulation. As a result, our parallel execution with an eight-node PC cluster achieves up to 5.8-fold speed-up.3. To estimate the worst-case delay caused by interrupts, which is required in the design of real-time systems, we devised O (FN) algorithms to analyze the worst-case miss increments of caches and branch predictors for a workload with N instructions and F interrupts. Furthermore, we devised a O (Nlog N)algorithm to calculate the delay itself accurately using CAS, which can be accelerated by parallelization, up to 9-fold with an eight-node PC cluster.

针对以微处理器为核心部件的先进IT系统，对周期精确仿真（CAS）的并行化和性能改进进行了研究。本研究的主要成果有以下几个方面：1.我们的并行CAS相结合的顺序执行模拟器产生近似的并行模拟的部分结果。为了避免这种顺序的顺序模拟器成为瓶颈，我们设计了一种加速技术来自动生成特定于每个工作负载的模拟器。该技术实现了高达34倍的指令级仿真性能的提高.本文提出了一种新的并行模拟方法，它将模拟过程沿时间轴划分为沿着多个区间，使各区间并行执行。由于区间间的依赖性，采用顺序模拟的方法，用前一区间的部分近似结果推测性地执行各区间，从而解决了区间间依赖性问题。结果表明，在一个8节点的PC集群上，并行执行的速度提高了5.8倍。为了估计中断引起的最坏情况下的延迟，这是在实时系统的设计中所需要的，我们设计了O（FN）算法来分析最坏情况下的未命中增量的缓存和分支预测的工作负载与N条指令和F个中断。此外，我们设计了一个O（Nlog N）的算法来计算延迟本身准确地使用CAS，它可以加速并行化，高达9倍的8节点PC集群。