Development of a sensor-node processor with four order of magnitude variable power dissipation

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This project developed a processor that realizes "ultra-low power operation" demanded to sensor nodes composing sensor networks. Also, device modeling and circuit techniques needed to implement the processor was developed. Evaluating the processor on a test chip fabricated in 65nm process, the processor archived 4.18pJ/cycle at 0.5V in a normal synchronized operation mode, and the energy dissipation was further reduced by introducing an asynchronous operation.