Massively Parallel Networks in 3D-Stacked Silicon Wafers

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With the continuing advances in VLSI technology, multiprocessor systems with tens to hundreds of processing elements are expected to rival today's supercomputers in the next decade. Systems consisting of a few tens to a million processing elements have indeed been described in the literature. The development of such large scale systems will make numerous applications such as multi-media, computer vision, and modeling of physical phenomena to be feasible on desk-top workstations. However, a major issue in designing large scale multiprocessor systems is the construction of a flexible interconnection network to provide efficient inter-processor communication.This research develops a hierarchically structured interconnection network, 'Tori connected mESHes' (TESH), which allows exploitation of computational locality as well as modular future expansion. Also, the network has reduced wiring and only a few ports per processor, features that are essential in cost-effective implementation of large scale computing systems. Further, it has a regular structure which makes addressing of nodes and message routing rather straightforward. The network also appears to permit 3-D stacked implementation. In part, this is due to the far fewer number of vertical wires needed than almost all known multi-computer networks. As is well known, parallelizing a problem is usually application-specific and system architecture dependent. Therefore, several applications such as sorting, merging, FFT, and convolution, have been mapped to the network as paradigms in.