Self-Reconfigufation Architecture of Mesh-Connected Network for Multiprocessor Systems and The Implemantation

多处理器系统网状网络自重构架构及实现

• 批准号: 11558032
• 负责人: HORIGUCHI Susumu
• 金额: $ 6.21万
• 依托单位: Japan Advanced Institute of Science and Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1999
• 资助国家: 日本
• 起止时间: 1999 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-11558032/
• 关键词: fault tolerance; mesh array network; self-reconfiguration; wafer scale integration; FPGA; シフト・バイパス自律再構成; VLSI・ULSI技術; シラト・バイパス自律再構成; VLSI再構成技術; 自律再構成ネットワーク

This research deals with the issue of reconfiguring network interconnection for mesh-connected processor arrays (mesh array) implemented in VLSI/WSI. For massively parallel systems, it is becoming necessary to develop self-reconfiguratopn architecture that can automatically reconfigure partially faulty systems. Many reconfiguration algorithms have been proposed to date, however, most of them are not suitable for the self-reconfiguration and little literature shows the hardware implementation of the architecture actually. In this research, we propose a hardware-oiented self- reconfiguration architecture based on simple schemes of column bypass and south directional rerouting, and show a hardware implementation of proposed architecture using FPGA. The main feature of the proposed self-reconfiguration architecture is that faulty processors are avoided by switchig mechanisum, which can be determined its desired function automatically using states of neighboring processors. Simulated result shows that the proposed self-reconfiguration architecture is that faulty processors are avoided by switching machanism, which can be determined its desired function automatically using states of neighboring processors. Simulated result shows that the proposed architecture achieves higher system yield than those of the previous archtectures in rectangular mesh arrays. We also implement the reconfiguration system in FPGA and have been discussed in performance of it. The hardware overhead of redundant circuits such as switches and control circuits shows less than 4 %, where hardware cost of a procesor, which includes a test circuit, is 50 Kgates.

本研究针对超大型积体电路/广域积体电路中网状处理器阵列的网路互连重构问题。对于大规模并行系统，有必要开发一种能够自动重构部分故障系统的自重构体系结构。目前已经提出了许多重构算法，但大多数算法都不适用于自重构，并且很少有文献给出该结构的硬件实现。在这项研究中，我们提出了一个面向硬件的自重构架构的基础上，简单的方案列旁路和南向重路由，并显示了一个硬件实现所提出的架构使用FPGA。提出的自重构结构的主要特点是，故障处理器避免切换mechanisum，它可以确定其所需的功能自动使用相邻处理器的状态。仿真结果表明，所提出的自重构体系结构通过切换机制来避免故障处理器的出现，切换机制可以根据相邻处理器的状态自动确定其期望功能。仿真结果表明，在矩形网格阵列中，该结构比以往的结构具有更高的系统成品率。在FPGA上实现了该重构系统，并对其性能进行了分析，其中包括测试电路的处理器的硬件开销为50 Kgates，而开关、控制电路等冗余电路的硬件开销小于4%。

项目成果

J.C.Lo, S.Horiguchi, edited: "IEEE Computer Society Press, ISBN 0-7695-0719-0(2001 Oct.)""Proc. the IEEE International Symposium on Defect and Fault Tolerance in VLSI System". 500 (2001)

J.C.Lo、S.Horiguchi 编辑：“IEEE Computer Society Press，ISBN 0-7695-0719-0（2001 年 10 月）”“Proc. the IEEE International Symposium on Defect and Fault Tolerance in VLSI System”。

T.Touyama, A.Takahashi and S.Horiguchi,: ""Optimal Location of High-Speed Facility in Heterogeneous Networks","Proc.IEEE Int'l Symp.on Parallel Architectures,Algorithms and Networks(ISPAN'2000),IEEEE CS Press,. Richardson, TX, U.S.A.. pp.246-251, (2000)

T.Touyama、A.Takahashi 和 S.Horiguchi，“异构网络中高速设施的最佳位置”，Proc.IEEE Intl Symp.on Parallel Architectures, Algorithms and Networks(ISPAN2000)，IEEEE

三浦 康之,阿部 亨,堀口 進,: ""階層型ネットワークTESHにおける仮想チャンネルフロー制御法","情報処理学会第125回計算機アーキテクチャ研究会,. vol.133-8,. 43-48 (1999)

Yasuyuki Miura、Toru Abe、Susumu Horiguchi，“分层网络 TESH 中的虚拟通道流量控制方法”，日本信息处理学会第 125 届计算机体系结构研究组，第 133-8, 43-48 (1999)

Y.Inoguchi, T.Matsuzawa, S.Horiguchi: "Cooling Scheme for 3D Stacked Mesh Array by Biased Shifting"Proc of IEEE High Performance Computing in Asia Conference. Goldcoast, Australia. 1-8 (2001)

Y.Inoguchi、T.Matsuzawa、S.Horiguchi：“Cooling Scheme for 3D Stacked Mesh Array by Biased Shifting”IEEE 高性能计算亚洲会议论文集。

Y. Miura, S. Horiguchi and, V, K. Jain: "^<II>Deadlock-free Routing of Hierachical Interconnection Network : TESH (in Japanese)^<II>"Journal of Information Processing of Japan. Vol. 41, No. 5. 1370-1378 (2000)

Y. Miura、S. Horiguchi 和 V、K. Jain：“^<II>分层互连网络的无死锁路由：TESH（日语）^<II>”日本信息处理杂志。