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Self-Reconfigurable Massively Parallel Computer on Stacked Wafers

堆叠晶圆上的自重构大规模并行计算机

基本信息

批准号：
05044090
负责人：
HORIGUCHI Susumu
金额：
$ 15.36万
依托单位：
JAPAN ADVANCED JNSTITUTE of SCIENCE and Technology, Hokuriku
依托单位国家：
日本
项目类别：
Grant-in-Aid for international Scientific Research
财政年份：
1993
资助国家：
日本
起止时间：
1993 至 1995
项目状态：
已结题

项目摘要

This research deals with a 3D-mesh array on stacked wafers and its fault tolerant architecture. The architecture of 3D-mesh arrays provides a self-reconfiguration of interconnections using a recursive shift scheme. Anuj Chandra et al. also proposed a reconfigurable algorithm for 3D 1/ track model based on a compensation path scheme that was originally proposed S.Y.Kung et al. The 3D 1/ track model was, however, discussed only from the theoretical view points of extension of the 2D 1/ track model. This paper examines its fault tolerant performance to obtain the system yield of a 3D-mesh array using a self-reconfiguration scheme.First, we reviews recent WSI devices to construct massively parallel computers and summarize the merit of WSI parallel computers. Next. we deal with the mesh-connected multiprocessor architecture and reconfiguration stategies to enhance the array yield for WSI implementation. Reconfiguration performance of a mesh-connected parallel computer is discussed by comparing it to previous works. WSI implementation of a cube-connected cycles (CCC) is addressed and its yield performance is discussed by taking into account the chip area of the PEs, switches, and links. We also propose a new interconnection network HCQ based on a crossed cube interconnection to reduce the diameter and the average distance of the interconnection network. The excellent network property of HCQ is theoretically investigated. Finally, we discussed a 3D-mesh array on stacked wafers for massively parallel computers. A reconfiguration algorithm based on a recursive shift scheme is proposed. Applying the recursive shift scheme to a 3D-mesh array, it is shown that the reconfiguration performance becomes high and provides the possibility to construct a massively parallel computer on stacked wafers like as the 3D-mesh array.

本研究探讨堆叠式晶圆上的三维网状阵列及其容错架构。三维网状阵列的架构提供了一个自我重新配置的互连使用递归移位方案。Anuj Chandra等人还提出了一种基于补偿路径方案的3D 1/ track模型的可重构算法，该补偿路径方案最初是由S. Y. Kung等人提出的。然而，3D 1/ track模型仅从2D 1/ track模型的扩展的理论观点进行了讨论。本文研究了它的容错性能，以获得一个三维网格阵列的系统yield使用自重构方案。首先，我们回顾了最近的WSI设备构建大规模并行计算机，总结了WSI并行计算机的优点。下一个我们处理网状连接的多处理器架构和重新配置策略，以提高阵列产量的WSI实现。通过与以往的工作进行比较，讨论了网状连接并行计算机的重构性能。WSI实现的立方体连接的周期（CCC）的地址和其产量性能进行了讨论，考虑到芯片面积的PE，开关，和链接。我们还提出了一种新的互连网络HCQ的基础上交叉立方体互连，以减少直径和平均距离的互连网络。从理论上研究了HCQ的优良网络特性。最后，我们讨论了大规模并行计算机的堆叠晶片上的三维网格阵列。提出了一种基于递归移位的重构算法。应用递归移位方案的三维网格阵列，它示出的重构性能变得很高，并提供了可能性，以构建一个大规模的并行计算机上堆叠的晶片一样的三维网格阵列。