Research on Wafer Scale Integrated Computer

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Since the integarted circuit was invented, researches and designers have been challenging to get much more circuits on a chip. Wafer Scale Integration(WSI)is one of promising technologies for developing massively parallel systems which satisfy the continuous increasing demand for computer power.The aim of this research is to study a novel architecture of Wafer Scale Computer. We already proposed hybrid systolic sorters which are suitable for WSI implementation. The hybrid sorter has a hierarchical redundancy network and is powerful architecture for fault tolerance. We also proposed a reconfigurable architecture for mesh-interconnection processing arrays. Our WSI architecture of array processors achieves both higher reliability and higher production yield.We have studied on WSI architectures of cube-connected cycle multiprocessor. Cube-connected cycle is one of promising network topologies for multiprocessor systems. Our placement scheme of processing elements performs higher yield than other schemes. Testing and testability in WSI systems is still remained problems.