Conduit Diffusion in Silicon on Silicide on Insulator substrates

绝缘体上硅（SOI）技术现在对未来几代集成电路芯片至关重要。SOI提供了更快的芯片操作、简化的制造技术和低功耗操作。它还提供了将整个电子系统集成到芯片上的可能性。在这种相对简单的基质上出现了非常新颖的变化。绝缘体上硅化硅（SSOI）衬底就是这样的衬底。所述衬底包括埋在活性硅下面的低电阻率层（硅化钨）。这一层的主要应用是作为欧姆触点和电流返回表面触点之前的横向电流流动。集成电路使用埋藏离子注入层实现此功能，但硅化物可将串联电阻降低2个数量级。因此，采用这种衬底可以大大降低双极和功率器件中的寄生电阻。SSOI提供了进一步的潜在优势，但尚未被利用。埋藏硅化物在结构上是多晶的，因此普通掺杂剂对硅的扩散将以晶界扩散的方式进行，且扩散速度较快。低热收支处理可用于将这些掺杂剂相对较远的距离移动，而不会干扰上覆硅中的其他掺杂剂剖面。然后采用短时间快速热退火法将扩散掺杂物从硅化物中析出，从而在硅中形成超浅结。这一切都可以在设备生产的近后端实现，确保严格控制所有结型，消除宽埋植入层并简化制造时间表。这项技术将为令人兴奋的新工艺和器件架构提供进一步的机会，从ic和微波器件到功率和智能功率晶体管，在单位成本和电子器件性能方面具有优势。因此，该合同的重点是对掺杂剂在硅化钨中的扩散进行详细的科学研究。灵敏的电子实验结构将被采用，这将允许在距离上准确地表征掺杂物的扩散。这对于提供扩散率数据、分离系数等至关重要，这将有助于设计未来的工艺和设备。还必须制定向埋藏硅化物层提供掺杂剂的策略。对于处理技术的近后端，这将需要在重新填充沟槽技术上进行变化。本项目将尝试使用一些填充材料来研究这种方法。该技术将导致超低的寄生抗性。因此，确保任何壕沟填充技术都能提供较低的附加阻力是适当的。因此，将采用钨填充沟槽，为功率器件和线性集成电路提供优化的衬底。该技术的潜力将通过一个相对简单的微波二极管来展示。二极管将在SSOI衬底上制造，并将表现出最小的寄生电容和电阻。在项目期间，可以在新合同或工业合作中开发基板和拟议技术，以解决智能电源/垂直电源器件、线性IC技术和高频元件的问题。

Silicon on Insulator (SOI) technology is now of critical importance to future generations of integrated circuit chips. SOI offers potentially faster chip operation, simplified manufacturing technology and low power operation. It also offers the possibility of integrating entire electronic systems on a chip. Very novel variations on this relatively simple substrate are emerging. The Silicon on Silicide on Insulator (SSOI) substrate is one such substrate. This substrate includes a low resistivity layer (tungsten silicide) buried under the active silicon. Primary applications of this layer would be as ohmic contacts and for lateral current flow of current prior to return to surface contacts. ICs use buried ion implanted layers for this function but the silicide offers 2 orders of magnitude reduction in series resistance. Parasitic resistance in bipolar and power devices can therefore be substantially reduced by employing this substrate. The SSOI offers further potential advantage which has not yet been exploited. The buried silicide is polycrystalline in structure and diffusion of common dopants for silicon will therefore be by grain boundary diffusion which will be rapid. Low thermal budget treatment may be used to move these dopants relatively long distance without disturbance of other dopant profiles in the overlying silicon. Short time rapid thermal anneal can then be employed to out diffuse dopant from the silicide to produce ultra-shallow junctions in the silicon. This can all be achieved at the near back end of the device production ensuring tight control of all junction profiles, elimination of wide buried implanted layers and simplification in the manufacturing schedule. This technology will provide further opportunity for exciting new process and device architectures with advantage offered in unit cost and electronic device performance over the spectrum from ICs and microwave devices to power and smart power transistors. The focus of this contract is therefore to conduct a detailed scientific investigation of dopant diffusion in tungsten silicide. Sensitive electronic experimental structures will be employed which will allow accurate characterisation of dopant diffusion over distance. This is vitally important to provide the diffusivity data, segregation coefficients etc which will allow design of future processes and devices. Strategy for supply of dopant to the buried silicide layer must also be developed. For near back end of processing technology this will require variations on refilled trench technology. This project will seek to investigate this approach using a number of refill materials. The technology will lead to ultra low parasitic resistance. It is therefore proper to ensure that any trench refill technology may offer low additional resistance. Trench refill with tungsten will therefore be undertaken to provide an optimised substrate for power devices and linear ICs. The potential of the technology will be demonstrated with a relatively simple microwave diode. The diode will be manufactured on the SSOI substrate and will exhibit minimised parasitic capacitance and resistance. Exploitation of the substrate and the proposed technology can develop in new contracts or industrial collaborations during the time of the project to address smart power/ vertical power devices, linear IC technology and high frequency components.