Conduit Diffusion in Silicon on Silicide on Insulator substrates

绝缘体基板上硅化物上硅中的导管扩散

• 批准号: EP/D060230/1
• 负责人: Brian Mervyn Armstrong
• 金额: $ 36.35万
• 依托单位: Queen's University Belfast
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2006
• 资助国家: 英国
• 起止时间: 2006 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FD060230%2F1
• 关键词: Conduit; Diffusion; Silicon; Silicide; Insulator

Silicon on Insulator (SOI) technology is now of critical importance to future generations of integrated circuit chips. SOI offers potentially faster chip operation, simplified manufacturing technology and low power operation. It also offers the possibility of integrating entire electronic systems on a chip. Very novel variations on this relatively simple substrate are emerging. The Silicon on Silicide on Insulator (SSOI) substrate is one such substrate. This substrate includes a low resistivity layer (tungsten silicide) buried under the active silicon. Primary applications of this layer would be as ohmic contacts and for lateral current flow of current prior to return to surface contacts. ICs use buried ion implanted layers for this function but the silicide offers 2 orders of magnitude reduction in series resistance. Parasitic resistance in bipolar and power devices can therefore be substantially reduced by employing this substrate. The SSOI offers further potential advantage which has not yet been exploited. The buried silicide is polycrystalline in structure and diffusion of common dopants for silicon will therefore be by grain boundary diffusion which will be rapid. Low thermal budget treatment may be used to move these dopants relatively long distance without disturbance of other dopant profiles in the overlying silicon. Short time rapid thermal anneal can then be employed to out diffuse dopant from the silicide to produce ultra-shallow junctions in the silicon. This can all be achieved at the near back end of the device production ensuring tight control of all junction profiles, elimination of wide buried implanted layers and simplification in the manufacturing schedule. This technology will provide further opportunity for exciting new process and device architectures with advantage offered in unit cost and electronic device performance over the spectrum from ICs and microwave devices to power and smart power transistors. The focus of this contract is therefore to conduct a detailed scientific investigation of dopant diffusion in tungsten silicide. Sensitive electronic experimental structures will be employed which will allow accurate characterisation of dopant diffusion over distance. This is vitally important to provide the diffusivity data, segregation coefficients etc which will allow design of future processes and devices. Strategy for supply of dopant to the buried silicide layer must also be developed. For near back end of processing technology this will require variations on refilled trench technology. This project will seek to investigate this approach using a number of refill materials. The technology will lead to ultra low parasitic resistance. It is therefore proper to ensure that any trench refill technology may offer low additional resistance. Trench refill with tungsten will therefore be undertaken to provide an optimised substrate for power devices and linear ICs. The potential of the technology will be demonstrated with a relatively simple microwave diode. The diode will be manufactured on the SSOI substrate and will exhibit minimised parasitic capacitance and resistance. Exploitation of the substrate and the proposed technology can develop in new contracts or industrial collaborations during the time of the project to address smart power/ vertical power devices, linear IC technology and high frequency components.

绝缘体上硅（SOI）技术现在对未来几代集成电路芯片至关重要。SOI提供了潜在的更快的芯片操作、简化的制造技术和低功率操作。它还提供了在芯片上集成整个电子系统的可能性。在这种相对简单的基质上出现了非常新颖的变化。绝缘体上硅化物上硅（SSOI）衬底就是这样的衬底之一。该衬底包括埋在有源硅下的低电阻率层（硅化钨）。该层的主要应用将是作为欧姆接触和用于电流在返回到表面接触之前的横向电流流动。IC使用掩埋离子注入层来实现此功能，但硅化物在串联电阻上提供了2个数量级的降低。因此，通过采用这种衬底，可以大大降低双极和功率器件中的寄生电阻。SSOI提供了尚未开发的进一步潜在优势。掩埋的硅化物在结构上是多晶的，因此硅的普通掺杂剂的扩散将通过晶界扩散进行，这将是快速的。低热预算处理可用于使这些掺杂剂移动相对长的距离，而不干扰上覆硅中的其它掺杂剂分布。然后可以采用短时间快速热退火来从硅化物中扩散掺杂剂，以在硅中产生超浅结。这一切都可以在器件生产的后端附近实现，确保严格控制所有结型，消除宽埋注入层，简化制造进度。该技术将为令人兴奋的新工艺和器件架构提供进一步的机会，并在从IC和微波器件到功率和智能功率晶体管的范围内提供单位成本和电子器件性能方面的优势。因此，该合同的重点是对硅化钨中的掺杂剂扩散进行详细的科学调查。敏感的电子实验结构将被采用，这将允许掺杂剂扩散的精确表征的距离。这对于提供扩散率数据、偏析系数等至关重要，这些数据将允许未来工艺和设备的设计。还必须开发用于向掩埋硅化物层供应掺杂剂的策略。对于接近后端的处理技术，这将需要对再填充沟槽技术进行变化。本项目将使用一些填充材料来研究这种方法。该技术将导致超低寄生电阻。因此，确保任何沟槽再填充技术可以提供低的附加电阻是适当的。因此，将采用钨进行沟槽填充，以提供用于功率器件和线性IC的优化基板。该技术的潜力将通过一个相对简单的微波二极管来证明。二极管将在SSOI衬底上制造，并将表现出最小的寄生电容和电阻。在项目期间，可以在新合同或工业合作中开发衬底和拟议技术，以解决智能功率/垂直功率器件、线性IC技术和高频元件。