Utilizing Serial Communication to Improve the Area Efficiency of FPGAs for Implementing Multi-Bit Processing Circuits

利用串行通信提高 FPGA 实现多位处理电路的面积效率

• 批准号: 327691-2012
• 负责人: Ye, Andy
• 金额: $ 1.31万
• 依托单位: Ryerson University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=572103
• 关键词: Utilizing; Serial; Communication; Improve; Area

The goal of this research is to improve the area efficiency of Field-Programmable Gate Array (FPGA) routing resources through the effective use of on-chip serial communication. Serial communication has been an effective method for increasing the area efficiency of inter-chip communications. For FPGAs, where a large number of highly flexible programmable wires are used to connect a set of highly programmable logic together, serial communication potentially can also be an effective method for improving the area efficiency of intra-chip communications. In particular, with ever-increasing logic capacity, FPGAs are being increasingly used to implement large arithmetic-intensive applications. As large arithmetic-intensive applications often contain a large proportion of datapath circuits --- circuits that are designed to process multiple-bit wide data --- FPGA routing resources are being increasingly used to transport multiple-bit wide signals from one computing element (such as a logic block, a DSP block, or a multi-bit addressable memory cell) to another. By sharing a common link among multiple bits of signals, serial communication can effectively reduce the number of wires that are required to transport these signals and consequently reduce the overall implementation area of FPGAs. In this work, we will characterize the area, performance, and power efficiency of serial communication networks on FPGAs. In particular, three types of serial communication networks will be investigated: un-pipelined, global-synchronously pipelined, and source-synchronously pipelined (including wave-pipelining and surfing) serial communication networks. We will develop new FPGA architectures and tools to efficiently incorporate these serial communication networks into the routing resources of FPGAs and empirically evaluate the effect of serial communication on the area, performance, and power efficiency of FPGAs.

本研究的目的是通过片上串口通信的有效利用，提高现场可编程门阵列布线资源的面积效率。串口通信已成为提高芯片间通信面积效率的有效方法。对于使用大量高度灵活的可编程导线将一组高度可编程的逻辑连接在一起的现场可编程门阵列而言，串行通信也可能成为提高芯片内通信的面积效率的有效方法。 特别是，随着逻辑容量的不断增加，现场可编程门阵列越来越多地被用于实现大型算术密集型应用。由于大型算术密集型应用通常包含很大比例的数据路径电路-被设计为处理多位宽数据的电路-正越来越多地使用FPGA布线资源来将多位宽信号从一个计算元件(例如逻辑块、DSP块或多位可寻址存储单元)传输到另一个计算元件。通过在多个信号比特之间共享一条公共链路，串行通信可以有效地减少传输这些信号所需的导线数量，从而减小了FPGA的总体实现面积。 在这项工作中，我们将对现场可编程门阵列上的串行通信网络的面积、性能和功率效率进行表征。特别是，将研究三种类型的串行通信网络：非流水线、全局同步流水线和源同步流水线(包括波浪流水线和冲浪)串行通信网络。我们将开发新的现场可编程门阵列架构和工具，将这些串行通信网络有效地整合到现场可编程门阵列的布线资源中，并经验性地评估串行通信对现场可编程门阵列面积、性能和功率效率的影响。