Utilizing Serial Communication to Improve the Area Efficiency of FPGAs for Implementing Multi-Bit Processing Circuits

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The goal of this research is to improve the area efficiency of Field-Programmable Gate Array (FPGA) routing resources through the effective use of on-chip serial communication. Serial communication has been an effective method for increasing the area efficiency of inter-chip communications. For FPGAs, where a large number of highly flexible programmable wires are used to connect a set of highly programmable logic together, serial communication potentially can also be an effective method for improving the area efficiency of intra-chip communications. In particular, with ever-increasing logic capacity, FPGAs are being increasingly used to implement large arithmetic-intensive applications. As large arithmetic-intensive applications often contain a large proportion of datapath circuits --- circuits that are designed to process multiple-bit wide data --- FPGA routing resources are being increasingly used to transport multiple-bit wide signals from one computing element (such as a logic block, a DSP block, or a multi-bit addressable memory cell) to another. By sharing a common link among multiple bits of signals, serial communication can effectively reduce the number of wires that are required to transport these signals and consequently reduce the overall implementation area of FPGAs. In this work, we will characterize the area, performance, and power efficiency of serial communication networks on FPGAs. In particular, three types of serial communication networks will be investigated: un-pipelined, global-synchronously pipelined, and source-synchronously pipelined (including wave-pipelining and surfing) serial communication networks. We will develop new FPGA architectures and tools to efficiently incorporate these serial communication networks into the routing resources of FPGAs and empirically evaluate the effect of serial communication on the area, performance, and power efficiency of FPGAs.