Utilizing Run-Time Reconfiguration to Reduce the Static Power Consumption of FPGAs for Mobile Applications

利用运行时重新配置来降低移动应用 FPGA 的静态功耗

• 批准号: RGPIN-2017-04405
• 负责人: Ye, Andy
• 金额: $ 1.75万
• 依托单位: Ryerson University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637195
• 关键词: Utilizing; Run; Time; Reconfiguration; Reduce

The goal of this research is to reduce the power consumption of FPGAs to the level of the lowest power consuming processors through the use of run-time reconfiguration. Run-time reconfiguration, the ability of an FPGA to change its functionality while under operation, has been successfully used in many commercial FPGAs to expand the logic capacity of FPGAs to beyond what can be manufactured by current silicon process technologies. For portable devices with limited battery power, however, the logic capacity of an FPGA is not limited by current process technologies but by the low power output of small batteries. Run-time reconfiguration potentially can allow FPGAs to gracefully trade performance for reduced power consumption in order to bring the power consumption of current low power FPGAs to the level of the lowest power consuming processors.

本研究的目标是通过使用运行时重配置，将FPGA的功耗降低到最低功耗处理器的水平。运行时重新配置是FPGA在运行时改变其功能的能力，已成功地用于许多商业FPGA中，以扩展FPGA的逻辑容量，使其超出当前硅工艺技术所能制造的范围。然而，对于电池电量有限的便携式设备，FPGA的逻辑容量不受当前工艺技术的限制，而是受小电池的低功率输出的限制。运行时重新配置可能允许FPGA优雅地以性能换取降低的功耗，以便使当前低功耗FPGA的功耗达到最低功耗处理器的水平。