Utilizing Run-Time Reconfiguration to Reduce the Static Power Consumption of FPGAs for Mobile Applications

本研究的目标是通过使用运行时重新配置将fpga的功耗降低到最低功耗处理器的水平。运行时重新配置，即FPGA在运行时改变其功能的能力，已成功地用于许多商用FPGA，以扩展FPGA的逻辑容量，超出当前硅工艺技术所能制造的范围。然而，对于电池电量有限的便携式设备，FPGA的逻辑容量不受当前工艺技术的限制，而是受小型电池的低功率输出的限制。运行时重新配置可能允许fpga优雅地交换性能以降低功耗，以便将当前低功耗fpga的功耗降低到最低功耗处理器的水平。fpga是实现各种数字应用的重要平台，因为它们的上市时间短，可重新编程和低非重复性工程成本。虽然fpga已经成功地应用于许多应用，包括数字信号处理、航空航天、医学成像、计算机视觉、语音识别和ASIC原型，但由于其高静态功耗，它们尚未广泛应用于移动应用。特别是，今天的低功耗fpga的静态功耗明显高于最低功耗处理器的静态功耗。因此，受限于小电池的有限功率输出，目前的移动设备主要限于使用低功耗处理器，尽管这些处理器具有极低的性能和能源效率，特别是与fpga相比。在这项工作中，我们将描述运行时重构对fpga的面积、性能和功率效率的影响。特别是，我们将开发新的FPGA区域和性能模型，以准确测量运行时重构对FPGA性能、动态和静态功耗的影响。然后，我们将开发新的FPGA架构和工具，以有效地利用移动应用程序功率约束下的运行时重构，并经验评估运行时重构对低功耗FPGA的面积、性能和功率效率的影响。

The goal of this research is to reduce the power consumption of FPGAs to the level of the lowest power consuming processors through the use of run-time reconfiguration. Run-time reconfiguration, the ability of an FPGA to change its functionality while under operation, has been successfully used in many commercial FPGAs to expand the logic capacity of FPGAs to beyond what can be manufactured by current silicon process technologies. For portable devices with limited battery power, however, the logic capacity of an FPGA is not limited by current process technologies but by the low power output of small batteries. Run-time reconfiguration potentially can allow FPGAs to gracefully trade performance for reduced power consumption in order to bring the power consumption of current low power FPGAs to the level of the lowest power consuming processors.*** FPGAs are an important platform for implementing a variety of digital applications due to their short time to market, re-programmability and low non-recurring engineering costs. While FPGAs have been successfully used in many applications including digital signal processing, aerospace, medical imaging, computer vision, speech recognition, and ASIC prototyping, they have not been widely used in mobile applications due to their high static power consumption. In particular, the static power consumption of today's low power FPGAs is significantly higher than the static power consumption of the lowest power consuming processors. Consequently, constrained by the limited power output of small batteries, current mobile devices are mainly limited to the use of low-power processors despite the fact that these processors have extremely low performance and energy efficiency especially when compared to FPGAs. *** In this work, we will characterize the effect of run-time reconfiguration on the area, performance, and power efficiency of FPGAs. In particular, we will develop new FPGA area and performance models to accurately measure the effect of run-time reconfiguration on the performance, dynamic and static power consumption of FPGAs. We will then develop new FPGA architectures and tools to effectively utilize run-time reconfiguration under the power constraint of mobile applications and empirically evaluate the effect of run-time reconfiguration on the area, performance and power efficiency of low power FPGAs.