Utilizing Serial Communication to Improve the Area Efficiency of FPGAs for Implementing Multi-Bit Processing Circuits

利用串行通信提高 FPGA 实现多位处理电路的面积效率

• 批准号: 327691-2012
• 负责人: Ye, Andy
• 金额: $ 1.31万
• 依托单位: Ryerson University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2012
• 资助国家: 加拿大
• 起止时间: 2012-01-01 至 2013-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=509359
• 关键词: Utilizing; Serial; Communication; Improve; Area

The goal of this research is to improve the area efficiency of Field-Programmable Gate Array (FPGA) routing resources through the effective use of on-chip serial communication. Serial communication has been an effective method for increasing the area efficiency of inter-chip communications. For FPGAs, where a large number of highly flexible programmable wires are used to connect a set of highly programmable logic together, serial communication potentially can also be an effective method for improving the area efficiency of intra-chip communications.

本研究的目标是通过有效利用片上串行通信来提高现场可编程门阵列（FPGA）布线资源的面积效率。串行通信是提高片间通信面积效率的有效方法。对于FPGA来说，大量高度灵活的可编程导线用于将一组高度可编程逻辑连接在一起，串行通信也可能是提高芯片内通信面积效率的有效方法。