Digital-intensive clocking and data recovery circuits for low-power scalable wireline transceivers

点击翻译按钮获取中文摘要

Globally, we are on the cusp of revolutionary changes in communications fueled by the use of high throughput computing based on datacenter computers on one side, and mobile computing platforms such as laptops, tablets and smartphones on the other. Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) technologies accompanied by increasing complexity of integrated-circuits has led to fast and efficient computing systems. These platforms demand off-chip data bandwidth with extremely low power consumption in order to conserve power, posing significant design challenges. This collaborative project between UBC and Intel will focus on addressing these challenges. This proposed research aims to develop advanced wireline integrated circuits (ICs) for low-power transceivers. The work to be accomplished in this project primarily involves a mix of modelling, design and measurement work. The target application is next-generation wireline solutions and products for the industry such as MIPI M-PHY, next-generation PCIE and USB, etc.