Probabilistic-based Ultra-Low Supply Voltage Noise-Tolerant Circuits and Systems Design

基于概率的超低电源电压噪声耐受电路和系统设计

• 批准号: RGPIN-2016-04603
• 负责人: Chen, Jie
• 金额: $ 2.62万
• 依托单位: University of Alberta
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637278
• 关键词: Probabilistic; based; Ultra; Low; Supply

Power consumption has become a key performance criterion for integrated circuit design, especially in battery-based portable systems. Decreasing supply voltage is one of the most efficient and universal techniques to reduce energy dissipation because power is proportional to the square of supply voltage. However, when CMOS devices are scaled down following Moore’s law, noise tolerance becomes the bottleneck for the viability of nanoscale circuits. Furthermore, the smaller noise margin in low-voltage CMOS systems renders them even more sensitive to noise. Soft faults (caused by inherent noise and signal coupling) and hard faults (caused by variability and defects of fabrication technologies) present an obvious problem in nanoscale circuits. Random and dynamic noise, however, do not decrease in the same proportion as supply voltage is scaled down, which becomes a major challenge for low-supply-voltage designs.

功耗已经成为集成电路设计的关键性能指标，特别是在基于电池的便携式系统中。降低电源电压是降低能耗的最有效和最普遍的技术之一，因为功率与电源电压的平方成正比。然而，当CMOS器件按摩尔定律缩小时，噪声容忍度成为纳米级电路生存的瓶颈。此外，低电压cmos系统中较小的噪声容限使其对噪声更加敏感。软故障(由固有噪声和信号耦合引起)和硬故障(由制造工艺的可变性和缺陷引起)是纳米级电路中的一个明显问题。然而，随机和动态噪声并没有随着电源电压的减小而成比例地降低，这成为低电源电压设计的主要挑战。