Enhancing Hardware Compilation for Reconfigurable Architectures using Machine Learning and Cloud Computing

可重构计算架构，如FPGA（现场可编程门阵列），正在广泛复兴，特别是在利润丰厚的云计算市场。FPGA是专用计算芯片，允许实现完全针对特定问题定制的电路，从而实现高性能和提高能效。像微软这样的软件公司已经通过极具影响力的Catapult项目将FPGA集成到他们的数据中心服务中，该项目使用FPGA来加速计算和网络处理。像英特尔这样的硬件制造商已经为这些市场开发了新的计算芯片，将联合收割机处理器和FPGA结合在一起。** 虽然FPGA提供了许多优势，但它们也带来了巨大的挑战。与软件编程不同，FPGA需要将程序编译成低级电路。这需要一个耗时、复杂的编译流程，该流程基于启发式方法，需要处理相互冲突的指标，即芯片面积、电路速度和功耗。大型设计的FPGA编译（CAD）通常需要数小时甚至数天的时间，但仍然无法提供所需的指标。工业开发人员花费多个人工月来确保设计符合这些指标。** 该提案的一个关键目标是应用机器学习技术来提高硬件设计过程的质量和速度。这种方法与现有的算法和算法形成鲜明对比，这些算法和算法在过去几年中的改进微不足道。而不是试图设计通用算法，我们将从知识库中学习有关电路模式及其与FPGA CAD流程的复杂交互。我们将通过并行评估CAD工具，通过不同基准的输入配置变化来生成这些知识。此外，我们将通过这种学习驱动的方法构建高质量的预测模型，以便在编译流程的各个阶段做出更好的映射决策。** 在本提案中，我们还将使用机器学习来解决可靠性问题，例如由于外部影响或制造缺陷而导致的现场芯片故障。为此，我们需要开发一套新的在线（运行时）算法来监控和调整电路，以响应动态事件。我们将在硬件中嵌入智能，以自我监控和自我适应不断变化的条件，而不是使用预先确定的策略。学习驱动的方法为硬件提供了响应无法在测试实验室中完全复制的不可预见事件和条件的能力。**通过该计划培训的HQP将获得结合机器学习，硬件设计和软件工程的独特技能。这在加拿大工业蓬勃发展的人工智能和硬件设计领域有很高的需求。

Reconfigurable computing architectures, such as FPGAs (Field Programmable Gate Arrays), are enjoying a widespread renaissance, particularly in the lucrative cloud computing market. FPGAs are application-specific computing chips that allow implementation of circuits that are fully tailored to a specific problem, resulting in high performance and improved energy efficiency. Software companies like Microsoft have integrated FPGAs into their data center services through the highly influential Catapult project that uses FPGAs for accelerating both computations and network processing. Hardware manufacturers like Intel have developed new computing chips for these markets that combine processors and FPGAs. ******Though FPGAs offer many advantages, they present significant challenges. Unlike software programming, FPGAs require compiling programs into low-level circuits. This requires a time-consuming, complex compilation flow built on heuristics which juggles conflicting metrics i.e. chip area, circuit speed, and power. It is not uncommon for an FPGA compilation (CAD) of a large design to take hours or even days while still not delivering the desired metrics. Industrial developers spend multiple man-months to ensure that the design meets these metrics. ******A key goal of this proposal is to apply machine learning techniques to improve the quality and speed of hardware design process. This approach is in stark contrast with existing algorithms and heuristics that have delivered negligible improvements over the past few years. Instead of attempting to design generic algorithms, we will learn from a repository of knowledge about circuit patterns and their complex interactions with the FPGA CAD flow. We will generate this knowledge by evaluating the CAD tools in parallel through variations in their input configurations across different benchmarks. Additionally, we will build high-quality predictive models through this learning-driven approach to make better mapping decisions at various stages of the compilation flow. ******In this proposal, we will also use machine learning to tackle reliability issues such as chip failures in the field due to external effects or manufacturing defects. To do this, we need to develop a new set of online (runtime) algorithms to monitor and adjust the circuits to respond to dynamic events. Instead of using pre-determined strategies, we will embed intelligence within the hardware to self-monitor and self-adapt to changing conditions. A learning-driven approach provides the hardware with the ability to respond to unforeseen events and conditions that cannot be exhaustively replicated in the testing labs.******The HQP trained through this program will acquire a blend of unique skills combining machine learning, hardware design, as well as software engineering. This is in high demand in the booming artificial intelligence and hardware design sectors of the Canadian industry.