Enhancing Hardware Compilation for Reconfigurable Architectures using Machine Learning and Cloud Computing

可重构计算体系结构，如现场可编程门阵列(现场可编程门阵列)，正在广泛复兴，特别是在利润丰厚的云计算市场。现场可编程门阵列是专用计算芯片，允许实现完全针对特定问题量身定做的电路，从而实现高性能和更高的能效。微软等软件公司通过极具影响力的Catapult项目将现场可编程门阵列集成到其数据中心服务中，该项目使用现场可编程门阵列来加速计算和网络处理。像英特尔这样的硬件制造商已经为这些市场开发了结合处理器和现场可编程门阵列的新计算芯片。*尽管现场可编程门阵列提供了许多优势，但它们也带来了巨大的挑战。与软件编程不同，现场可编程门阵列需要将程序编译成低电平电路。这需要建立在启发式算法基础上的耗时的复杂编译流程，该流程在芯片面积、电路速度和功率等相互冲突的指标之间进行权衡。大型设计的FPGA编译(CAD)花费数小时甚至数天的时间，但仍无法提供所需的指标，这并不少见。工业开发人员花了数个人月的时间来确保设计符合这些指标。*这项提议的一个关键目标是应用机器学习技术来提高硬件设计过程的质量和速度。这种方法与现有的算法和启发式方法形成了鲜明对比，在过去的几年里，这些算法和启发式方法带来的改进微不足道。我们将不再尝试设计通用算法，而是从电路图案及其与FPGA CAD流程的复杂交互的知识存储库中学习。我们将通过在不同基准测试中对CAD工具的输入配置变化进行并行评估来生成这些知识。此外，我们将通过这种学习驱动的方法构建高质量的预测模型，以在编译流程的各个阶段做出更好的映射决策。*在这份提案中，我们还将使用机器学习来解决可靠性问题，例如由于外部影响或制造缺陷导致的现场芯片故障。要做到这一点，我们需要开发一套新的在线(运行时)算法来监控和调整电路，以响应动态事件。我们将在硬件中嵌入智能，以自我监控和自我适应不断变化的条件，而不是使用预先确定的策略。学习驱动的方法为硬件提供了应对不可预见的事件和条件的能力，这些事件和条件无法在测试实验室中完全复制。*通过该计划培训的HQP将获得结合机器学习、硬件设计和软件工程的独特技能。在加拿大蓬勃发展的人工智能和硬件设计行业，这一需求很高。

Reconfigurable computing architectures, such as FPGAs (Field Programmable Gate Arrays), are enjoying a widespread renaissance, particularly in the lucrative cloud computing market. FPGAs are application-specific computing chips that allow implementation of circuits that are fully tailored to a specific problem, resulting in high performance and improved energy efficiency. Software companies like Microsoft have integrated FPGAs into their data center services through the highly influential Catapult project that uses FPGAs for accelerating both computations and network processing. Hardware manufacturers like Intel have developed new computing chips for these markets that combine processors and FPGAs. ******Though FPGAs offer many advantages, they present significant challenges. Unlike software programming, FPGAs require compiling programs into low-level circuits. This requires a time-consuming, complex compilation flow built on heuristics which juggles conflicting metrics i.e. chip area, circuit speed, and power. It is not uncommon for an FPGA compilation (CAD) of a large design to take hours or even days while still not delivering the desired metrics. Industrial developers spend multiple man-months to ensure that the design meets these metrics. ******A key goal of this proposal is to apply machine learning techniques to improve the quality and speed of hardware design process. This approach is in stark contrast with existing algorithms and heuristics that have delivered negligible improvements over the past few years. Instead of attempting to design generic algorithms, we will learn from a repository of knowledge about circuit patterns and their complex interactions with the FPGA CAD flow. We will generate this knowledge by evaluating the CAD tools in parallel through variations in their input configurations across different benchmarks. Additionally, we will build high-quality predictive models through this learning-driven approach to make better mapping decisions at various stages of the compilation flow. ******In this proposal, we will also use machine learning to tackle reliability issues such as chip failures in the field due to external effects or manufacturing defects. To do this, we need to develop a new set of online (runtime) algorithms to monitor and adjust the circuits to respond to dynamic events. Instead of using pre-determined strategies, we will embed intelligence within the hardware to self-monitor and self-adapt to changing conditions. A learning-driven approach provides the hardware with the ability to respond to unforeseen events and conditions that cannot be exhaustively replicated in the testing labs.******The HQP trained through this program will acquire a blend of unique skills combining machine learning, hardware design, as well as software engineering. This is in high demand in the booming artificial intelligence and hardware design sectors of the Canadian industry.