Algorithms and Architectures for Digital Communications

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The central theme of the proposed research is algorithms, parallel VLSI architectures and system-on-chip (SoC) implementations of wireless baseband communication systems and certain types of network-connected head-end cryptographic security hardware. In the domain of emerging wireless technologies few, if any, technologies hold more promise at improving cost and performance than CMOS SoC realizations with significant integrated embedded-memory subsystems that are co-designed at the algorithm and architecture levels to exploit the parallel structure of the matrix-vector algorithms required.*******The goal of this research is to develop low-complexity signal processing algorithms for wireless baseband and homomorphic encryption algorithms that have both provably good performance and an efficient microelectronic realization. A methodology to address this research challenge lies in very promising recent progress in reformulating parallel algorithms for low clock rate, embedded-memory Quasi-Cyclic Low-Density Parity-Check (LDPC) decoders that support multi-Gb/s performance. We plan to further develop the concepts in an 802.11ad compliant Quasi-Cyclic LDPC CMOS prototype, though the concepts are very attractive for other applications. For example, our parallel Quasi-Cyclic LDPC algorithm would enable GPU-based realizations with block sizes of 10^6 for use in Continuous-Variable Quantum Key Distribution (CVQKD) protocols advancing current capabilities significantly. ******With embedded memory now dominating the area and cost of SoC systems in this domain, we further advance our research by developing new insights into the realization of LDPC and FFT engines that exploit the memory-based nature of the implementation but are co-designed at the system, algorithm and architecture levels with improved performance.******Fully Homomorphic Encryption (FHE) is a recently developed mathematical technique that allows mathematical operations (both multiplication and addition) on encrypted numbers. Central to practical future realizations, ciphertext multiplication operations are crucial for almost every envisioned application and especially applications that require searching and matching where dictionaries are large. Therefore, faster polynomial multiplication techniques, using Chinese Remainder Theorem (CRT)-based and embedded memory-based innovations, promising improved execution times will be investigated. Furthermore, architecture and circuit design innovations in the context of area and power-efficient VLSI implementations will be designed, fabricated and tested to demonstrate practical applications.******This work will impact the way future wireless systems for entertainment, education and commerce are designed and implemented improving the cost and performance of wireless systems that transport next generation data, video and secure information services.