High-Performance Hardware-Accelerated Private Computation

完全同态加密（FHE）是一种加密数据的方法，使用户能够在数据上执行任意操作序列，例如加法或乘法，而无需解密。对加密数据进行计算的能力非常有用，因为它允许在不受信任的基于云的机器上对敏感的个人数据执行服务，而不会损害数据的安全性或隐私性。使用底层的基于格子的数学来执行数学运算需要耗费大量的计算时间和内存。到目前为止，这些计算成本阻碍了FHE技术在许多大规模的实际应用中的实际应用。突破这一计算成本障碍是提出的研究计划所解决的核心研究挑战。为了以更高的计算效率实现FHE，已经使用了许多不同的数学基础，并且正在开发中。加速FHE方案的一种常用技术是将多个数据位或操作数同时加密到使用的单个多项式中，或者利用利用FHE矩阵代数运算中固有数学结构的并行计算硬件。图形处理单元（gpu）和现场可编程门阵列（fpga）都被用作硬件平台，以这些方式加速FHE方案。每种硬件平台都存在挑战。例如，加密数据比明文数据需要更多的内存存储和带宽，在高性能应用程序中，它很容易超过现成的fpga的能力。由最先进的CMOS片上系统（SoC）技术实现的用于FHE的单用途专用硬件加速器将提供大大加速的性能，从而实现广泛的企业级应用。FHE尚未针对基于硬件的加速进行优化的一个重要应用是为非常大的多维数据集实现核逻辑回归机器学习模型。核逻辑回归是一种分类技术，它给出一组输入，计算输入属于由复杂决策面定义的某一类的概率。这个操作是许多机器学习应用的关键。本研究计划的目标是确定可扩展的VLSI硬件加速架构和电路，这些架构和电路可以将在加密数据上运行机器学习推理模型所需的执行时间减少两个数量级，从而使目前需要数小时才能解决的机器学习问题在几分钟内解决。如果实现这一目标，它将为广泛实施安全、私有、经济高效、基于云的机器学习模型的FHE实现铺平道路，从而保证数据、模型和生成的推论的安全性和隐私性。

Fully homomorphic encryption (FHE) is a way of encrypting data that enables users to perform an arbitrary sequence of operations, such as addition or multiplication, on the data without having to decrypt to do so. The capacity to compute on encrypted data is extremely useful, as it allows for services to be performed on sensitive personal data on an untrusted cloud-based machine without ever compromising either the security or privacy of the data during. Performing the mathematical operations using the underlying lattice-based mathematics uses a great deal of compute time and memory. Until now, these computational costs have held back FHE technology from practical use in many large-scale, real-world applications.  Breaking through this compute cost barrier is the core research challenge addressed by the proposed research program. Many different mathematical foundations have been used and are in development to realize FHE at greater computational efficiencies. A common technique to accelerate an FHE scheme is to encrypt multiple bits of data or operands simultaneously into a single polynomial used, or to utilize parallel computational hardware that exploits the inherent mathematical structure found in FHE matrix algebra operations. Both graphic processing units (GPUs) and field-programmable gate arrays (FPGAs) have been used as hardware platforms to accelerate FHE schemes in these ways. Challenges exist for each of these hardware platforms. For example, encrypted data requires significantly more memory storage and bandwidth than plaintext data, to the point where it easily exceeds the capabilities of off-the-shelf FPGAs in high-performance applications. Single-purpose, dedicated, hardware accelerators for FHE as realized by state-of-the-art CMOS system-on-chip (SoC) technologies will provide greatly accelerated performance enabling widespread enterprise-scale applications. An important application of FHE that has not yet been optimized for hardware-based acceleration is the implementation of kernel logistic regression machine learning models for very large multi-dimensional data sets. Kernel logistic regression is a classification technique which, given a set of inputs, calculates the probability that the input belongs to a certain class as defined by a complex decision surface.  This operation is key to many machine learning applications.  The goal of this research program is identify scalable, VLSI hardware acceleration architectures and circuits that can reduce the execution time taken to run machine learning inference models on encrypted data by two orders of magnitude, enabling machine learning problems that currently take hours to be solved in minutes. If this is achieved, it would pave the way for widespread implementation of secure, private, cost-effective, cloud-based FHE implementations of machine learning models that guarantee the security and privacy of the data, the models and the inferences generated.