High-Performance Hardware-Accelerated Private Computation

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Fully homomorphic encryption (FHE) is a way of encrypting data that enables users to perform an arbitrary sequence of operations, such as addition or multiplication, on the data without having to decrypt to do so. The capacity to compute on encrypted data is extremely useful, as it allows for services to be performed on sensitive personal data on an untrusted cloud-based machine without ever compromising either the security or privacy of the data during. Performing the mathematical operations using the underlying lattice-based mathematics uses a great deal of compute time and memory. Until now, these computational costs have held back FHE technology from practical use in many large-scale, real-world applications.  Breaking through this compute cost barrier is the core research challenge addressed by the proposed research program. Many different mathematical foundations have been used and are in development to realize FHE at greater computational efficiencies. A common technique to accelerate an FHE scheme is to encrypt multiple bits of data or operands simultaneously into a single polynomial used, or to utilize parallel computational hardware that exploits the inherent mathematical structure found in FHE matrix algebra operations. Both graphic processing units (GPUs) and field-programmable gate arrays (FPGAs) have been used as hardware platforms to accelerate FHE schemes in these ways. Challenges exist for each of these hardware platforms. For example, encrypted data requires significantly more memory storage and bandwidth than plaintext data, to the point where it easily exceeds the capabilities of off-the-shelf FPGAs in high-performance applications. Single-purpose, dedicated, hardware accelerators for FHE as realized by state-of-the-art CMOS system-on-chip (SoC) technologies will provide greatly accelerated performance enabling widespread enterprise-scale applications. An important application of FHE that has not yet been optimized for hardware-based acceleration is the implementation of kernel logistic regression machine learning models for very large multi-dimensional data sets. Kernel logistic regression is a classification technique which, given a set of inputs, calculates the probability that the input belongs to a certain class as defined by a complex decision surface.  This operation is key to many machine learning applications.  The goal of this research program is identify scalable, VLSI hardware acceleration architectures and circuits that can reduce the execution time taken to run machine learning inference models on encrypted data by two orders of magnitude, enabling machine learning problems that currently take hours to be solved in minutes. If this is achieved, it would pave the way for widespread implementation of secure, private, cost-effective, cloud-based FHE implementations of machine learning models that guarantee the security and privacy of the data, the models and the inferences generated.