Algorithms and Architectures for Digital Communications
数字通信算法和架构
基本信息
- 批准号:RGPIN-2015-05376
- 负责人:
- 金额:$ 2.7万
- 依托单位:
- 依托单位国家:加拿大
- 项目类别:Discovery Grants Program - Individual
- 财政年份:2016
- 资助国家:加拿大
- 起止时间:2016-01-01 至 2017-12-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
The central theme of the proposed research is algorithms, parallel VLSI architectures and system-on-chip (SoC) implementations of wireless baseband communication systems and certain types of network-connected head-end cryptographic security hardware. In the domain of emerging wireless technologies few, if any, technologies hold more promise at improving cost and performance than CMOS SoC realizations with significant integrated embedded-memory subsystems that are co-designed at the algorithm and architecture levels to exploit the parallel structure of the matrix-vector algorithms required.
The goal of this research is to develop low-complexity signal processing algorithms for wireless baseband and homomorphic encryption algorithms that have both provably good performance and an efficient microelectronic realization. A methodology to address this research challenge lies in very promising recent progress in reformulating parallel algorithms for low clock rate, embedded-memory Quasi-Cyclic Low-Density Parity-Check (LDPC) decoders that support multi-Gb/s performance. We plan to further develop the concepts in an 802.11ad compliant Quasi-Cyclic LDPC CMOS prototype, though the concepts are very attractive for other applications. For example, our parallel Quasi-Cyclic LDPC algorithm would enable GPU-based realizations with block sizes of 10^6 for use in Continuous-Variable Quantum Key Distribution (CVQKD) protocols advancing current capabilities significantly.
With embedded memory now dominating the area and cost of SoC systems in this domain, we further advance our research by developing new insights into the realization of LDPC and FFT engines that exploit the memory-based nature of the implementation but are co-designed at the system, algorithm and architecture levels with improved performance.
Fully Homomorphic Encryption (FHE) is a recently developed mathematical technique that allows mathematical operations (both multiplication and addition) on encrypted numbers. Central to practical future realizations, ciphertext multiplication operations are crucial for almost every envisioned application and especially applications that require searching and matching where dictionaries are large. Therefore, faster polynomial multiplication techniques, using Chinese Remainder Theorem (CRT)-based and embedded memory-based innovations, promising improved execution times will be investigated. Furthermore, architecture and circuit design innovations in the context of area and power-efficient VLSI implementations will be designed, fabricated and tested to demonstrate practical applications.
This work will impact the way future wireless systems for entertainment, education and commerce are designed and implemented improving the cost and performance of wireless systems that transport next generation data, video and secure information services.
拟议的研究的中心主题是算法,并行VLSI架构和片上系统(SoC)实现的无线基带通信系统和某些类型的网络连接的头端加密安全硬件。在新兴的无线技术领域,很少有(如果有的话)技术比CMOS SoC实现在提高成本和性能方面更有希望,CMOS SoC实现具有重要的集成嵌入式存储器子系统,这些子系统在算法和架构级别进行协同设计,以利用所需的矩阵向量算法的并行结构。
本研究的目标是开发低复杂度的无线基带信号处理算法和同态加密算法,具有可证明的良好性能和有效的微电子实现。一种方法来解决这个研究挑战在于非常有前途的最近的进展,重新制定并行算法的低时钟速率,嵌入式存储器准循环低密度奇偶校验(LDPC)解码器,支持多Gb/s的性能。我们计划在符合802.11ad标准的准循环LDPC CMOS原型中进一步开发这些概念,尽管这些概念对其他应用非常有吸引力。例如,我们的并行准循环LDPC算法将使基于GPU的实现具有10^6的块大小,用于连续可变量子密钥分发(CVQKD)协议,从而显著提高当前的能力。
随着嵌入式存储器现在在这一领域的SoC系统的面积和成本占主导地位,我们进一步推进我们的研究,通过开发新的见解LDPC和FFT引擎的实现,利用基于存储器的性质的实施,但在系统,算法和体系结构级别的协同设计,提高性能。
全同态加密(FHE)是最近开发的一种数学技术,允许对加密数字进行数学运算(乘法和加法)。密文乘法运算是未来实际实现的核心,对于几乎所有设想的应用程序都至关重要,特别是需要在字典很大的情况下进行搜索和匹配的应用程序。因此,更快的多项式乘法技术,使用中国剩余定理(CRT)为基础的和嵌入式存储器为基础的创新,有望改善执行时间将被调查。此外,架构和电路设计创新的背景下,面积和功率效率的超大规模集成电路实现将设计,制造和测试,以展示实际应用。
这项工作将影响未来娱乐、教育和商业无线系统的设计和实施方式,从而提高传输下一代数据、视频和安全信息服务的无线系统的成本和性能。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Gulak, Glenn其他文献
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
- DOI:
10.1109/tcsi.2014.2380637 - 发表时间:
2015-03-01 - 期刊:
- 影响因子:5.1
- 作者:
Neshatpour, Katayoun;Shabany, Mahdi;Gulak, Glenn - 通讯作者:
Gulak, Glenn
Gulak, Glenn的其他文献
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{{ truncateString('Gulak, Glenn', 18)}}的其他基金
High-Performance Hardware-Accelerated Private Computation
高性能硬件加速私有计算
- 批准号:
RGPIN-2020-05807 - 财政年份:2022
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
High-Performance Hardware-Accelerated Private Computation
高性能硬件加速私有计算
- 批准号:
RGPIN-2020-05807 - 财政年份:2021
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
High-Performance Hardware-Accelerated Private Computation
高性能硬件加速私有计算
- 批准号:
RGPIN-2020-05807 - 财政年份:2020
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
Algorithms and Architectures for Digital Communications
数字通信算法和架构
- 批准号:
RGPIN-2015-05376 - 财政年份:2019
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
Algorithms and Architectures for Digital Communications
数字通信算法和架构
- 批准号:
RGPIN-2015-05376 - 财政年份:2018
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
Market Assessment for Rapid Bacterial Identification Diagnostic
快速细菌鉴定诊断的市场评估
- 批准号:
531911-2018 - 财政年份:2018
- 资助金额:
$ 2.7万 - 项目类别:
Idea to Innovation
Custom FPGA System for Intelligent Bed Sheet Patient Monitor
用于智能床单病人监护仪的定制 FPGA 系统
- 批准号:
522726-2017 - 财政年份:2017
- 资助金额:
$ 2.7万 - 项目类别:
Engage Grants Program
Algorithms and Architectures for Digital Communications
数字通信算法和架构
- 批准号:
RGPIN-2015-05376 - 财政年份:2017
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
Algorithms and Architectures for Digital Communications
数字通信算法和架构
- 批准号:
RGPIN-2015-05376 - 财政年份:2015
- 资助金额:
$ 2.7万 - 项目类别:
Discovery Grants Program - Individual
A Wireless CMOS Device for Rapid Point-of-Care Diagnosis of Bacterial Infections and Antibiotic Susceptibility Profiling
用于细菌感染快速护理诊断和抗生素敏感性分析的无线 CMOS 设备
- 批准号:
462274-2014 - 财政年份:2015
- 资助金额:
$ 2.7万 - 项目类别:
Collaborative Health Research Projects
相似海外基金
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