Realistic fault modelling to enable optimization of low power IoT and Cognitive fault-tolerant computing systems

现实故障建模可优化低功耗物联网和认知容错计算系统

• 批准号: EP/T023244/1
• 负责人: Asen Asenov
• 金额: $ 56.86万
• 依托单位: University of Glasgow
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2021
• 资助国家: 英国
• 起止时间: 2021 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FT023244%2F1
• 关键词: Realistic; fault; modelling; enable; optimization

For future ICT industry, the elephant in the room is Internet of Things (IoT) and Artificial Intelligence (AI). They are driving the fourth industrial revolution that is profoundly changing how we live and interact. The main issues for IoT and AI have been identified as: power, security, and cost. This project is co-created with the industrial partners and focuses on the power issue. One of the most effective way for reducing power is by lowering the operation voltage, Vg, towards the transistor threshold voltage, Vth. This has motivated recently extensive research in near threshold voltage computing. As Vg approaches Vth, the operation window (Vg-Vth) reduces and the system will be increasingly vulnerable to instability in Vth: a small rise in Vth can effectively switch off a transistor. Instability causes faults in operation, such as read and write errors in SRAM and digital timing errors. It is a limiting factor for how low (Vg-Vth) and, in turn, how much power consumption can be reduced.One of the critical tasks for low power system optimization is to minimise operation voltage and power consumption that will deliver specified yield 'Y' in 'X' years at a temperature below 'T'. To complete this optimization, designers need a fault analysis model that gives the time evolution of the probability distribution of Vth and driving current, Id, at a given distance from their target values. The further Vth and Id depart from their target values, the more likely a circuit will fail.Despite of decades of research, a reliable fault model is still not available. Indeed, in a recent review, the lack of realistic fault model tops the list of challenges for Cognitive Computing System design. Although the need for this model is clear, even world-leading EDA suppliers and foundries cannot deliver the model and current SPICE models simply do not include Jitter. This is related to weaknesses of previous research, including statistically inconsistent bottom-up methodology, limited time window, weak model verification criterion, and the neglect of the interaction of different instability sources.The fabless UK IC-design companies are using foundries for their chip fabrication. Software is the essential bridge between designers and foundries. As there are no generally accepted realistic fault models at present, designers have to rely on adding a guard-band (design margins) obtained from empirical 'worst case guess'. This contributes to the substantial discrepancy between design and Si performance. As CMOS nodes are downscaled to nano-meter range, the stochastic spreading of device parameters increases dramatically this discrepancy, which has been identified as a major challenge for optimizing the design of low power IoT and Cognitive Computing Systems.The aim of this project is to provide the world first test-proven fault model that enables statistical, dynamic, and quantitative analysis of fault rate and in turn the optimization of low power IoT and Cognitive Computing Systems. Novel techniques and methodologies will be employed to overcome the weakness of early works, including a top-down approach to remove device selection, advanced data acquisition method for long time window, qualifying the model by prediction capability, covering the interactions between different sources of instabilities. The developed model will be tested against Si performance of real circuits together with the industrial project partners. If successful, it will deliver a paradigm shift from one-size-fit-all to application specific fault analysis and optimization, reducing power and time-to-market.

对于未来的ICT产业来说，房间里的大象是物联网（IoT）和人工智能（AI）。他们正在推动第四次工业革命，深刻改变我们的生活和互动方式。物联网和人工智能的主要问题被确定为：功耗、安全性和成本。该项目是与产业伙伴共同创建的，重点关注电力问题。降低功耗最有效的方法之一是将工作电压 Vg 降低至晶体管阈值电压 Vth。这激发了最近对近阈值电压计算的广泛研究。当 Vg 接近 Vth 时，工作窗口 (Vg-Vth) 会减小，系统将越来越容易受到 Vth 不稳定的影响：Vth 的小幅上升可以有效地关断晶体管。不稳定会导致操作故障，例如 SRAM 读写错误和数字时序错误。它是 (Vg-Vth) 有多低以及功耗可以降低多少的限制因素。低功耗系统优化的关键任务之一是最大限度地降低工作电压和功耗，从而在低于“T”的温度下在“X”年内实现指定的产量“Y”。为了完成此优化，设计人员需要一个故障分析模型，该模型给出了在距目标值给定距离处 Vth 和驱动电流 Id 的概率分布随时间的演变。 Vth 和 Id 偏离目标值越远，电路发生故障的可能性就越大。尽管经过数十年的研究，仍然没有可靠的故障模型。事实上，在最近的一篇评论中，缺乏现实的故障模型是认知计算系统设计面临的首要挑战。尽管对该模型的需求是明确的，但即使是世界领先的 EDA 供应商和代工厂也无法提供该模型，并且当前的 SPICE 模型根本不包括抖动。这与先前研究的弱点有关，包括统计上不一致的自下而上方法、有限的时间窗口、薄弱的模型验证标准以及忽略不同不稳定源的相互作用。英国无晶圆厂IC设计公司正在使用代工厂进行芯片制造。软件是设计师和铸造厂之间的重要桥梁。由于目前没有普遍接受的现实故障模型，设计人员必须依靠添加从经验“最坏情况猜测”中获得的保护带（设计裕度）。这导致了设计和硅性能之间的巨大差异。随着 CMOS 节点尺寸缩小到纳米范围，器件参数的随机分布极大地增加了这种差异，这已被认为是优化低功耗物联网和认知计算系统设计的主要挑战。该项目的目的是提供世界上第一个经过测试验证的故障模型，能够对故障率进行统计、动态和定量分析，从而优化低功耗物联网和认知计算系统。 认知计算系统。将采用新颖的技术和方法来克服早期工作的弱点，包括自上而下的方法来消除设备选择、先进的长时间窗口数据采集方法、通过预测能力来限定模型、涵盖不同不稳定源之间的相互作用。开发的模型将与工业项目合作伙伴一起针对实际电路的硅性能进行测试。如果成功，它将实现从一刀切到特定应用故障分析和优化的范式转变，从而降低功耗并缩短上市时间。