基于介电弛豫时间模型的硅基GaN功率开关器件动态导通电阻特性及控制技术研究

由于优良的电学特性和具备大规模生产潜力，硅基GaN HEMT被认为是下一代高效、高频功率开关最有竞争力的替代者。本申请项目以研究硅基GaN HEMT动态导通电阻退化这一限制器件实用化的瓶颈问题为切入点，以弄清相关器件物理、发展具有高动态功率因数的硅基GaN功率开关器件制备技术为目标，创新提出开展基于介电弛豫时间模型的动态导通电阻特性及控制技术研究。主要研究内容包括大失配衬底上GaN HEMT缓冲层中陷阱态的物理行为、HEMT器件动态导通电阻退化的规律、缓冲层的低浓度p型掺杂对动态导通电阻的影响、缓冲层接地的新型硅基GaN HEMT功率开关器件等。研制出高性能硅基GaN功率开关器件，耐压大于1 kV、静态比导通电阻小于1.2毫欧厘米平方、600 V工作电压下动态导通电阻的上升小于50%，验证所建立的GaN HEMT动态导通电阻退化模型的正确性，加深对宽禁带半导体材料物理和器件物理的理解。

Due to the unique material properties and the capability for massive production, GaN HEMT on silicon substrate is believed to be the candidate of the next generation high efficiency and high frequency power switches. In this project, we would study the degradation phenomenon of the dynamic on-resistance in GaN HEMT on silicon substrate, try to reveal the underlying device physics, establishing the degradation model based on dielectric relaxation and develop the device technology for fabricating HEMT devices with high dynamic power figure of merit. The main research points include: the behavior of the trap states in the buffer layer of GaN HEMT on silicon substrate with large lattice mismatch, the degradation rule of the dynamic on-resistance, low density p-type doping of the buffer and the effect on the dynamic on-resistance, novel HEMT structure on silicon substrate with grounded buffer, etc. The fabricated high performance GaN power switch on silicon substrate is expected to deliver an off-state breakdown voltage larger 1 kV, a static specific on-resistance smaller than 1.2 milliohm centimeter square, a small increase of the dynamic on-resistance of about 50% under 600 V operation voltage, which would further confirm the accuracy of the established degradation model of the dynamic on-resistance in GaN power switch device and enhance the understanding of the material and device physics of wide band gap semiconductors.