Research on Layout, Interconnection, and Testing

本研究涵盖了超大规模集成电路的物理设计问题：宏单元， 基于自定义芯片布局，VLSI内部和之间的互连 芯片和可测试性设计。 布局问题是 在分层自动构建块布局中考虑 系统 问题是时序驱动的布局和优化 电源和接地网的布局。 后一个问题被考虑 对于三个金属层的情况。 理论和算法 联网问题正在研究中;以及两个具体的 问题正在得到解决。 它们是：三维模块 互连，包括长度和空间的估计，以及全局 详细路线 也被考虑的问题， 用于长线为主的定制芯片的布线方法， 用于晶片级集成的布线。 界面研究 布局和测试之间的关系正在得到解决。 特别是， 验证可测试性设计的假设， 通过布局减少难以检测的故障， 研究了 计算几何学被用来理解 设计可修复阵列的问题。

This research covers VLSI physical design problems: macrocell- based custom chip layout, interconnection within and between VLSI chips, and design for testability. Layout problems are considered within a hierarchical automatic building-block layout system. The problems are on timing-driven layout and optimum layout of power and ground nets. The later problem is considered for the case of three metal layers. Theory and algorithms for interconnection problems are being pursued; and two specific problems are being solved. These are: three-dimensional module interconnect including estimates of length and space, and global and detailed routing. Also being considered are problems in routing methodology for long-wire dominated custom chips and routing for wafer-scale integration. Research at the interface between layout and testing is being addressed. In particular, validation of assumptions made for design for testability and reduction of hard-to-detect faults through layout are being investigated. Computational geometry is being used to understand the problem of designing repairable arrays.