An Optoelectronic Integrated Circuit (OEIC) Galium Arsenide Receiver on a Silicon Substrate

一种全单片集成接收机芯片的研制 1.3并且提出了1.55微米的光纤波长。 芯片 将在Si衬底上制造，使得传统的双极 MOSFET技术可用于构建所有的 electronics. 我们将采用创新的方法， 硅上的高质量InP和相关化合物外延层 印刷受体. 氢化物VPE技术将用于 In（x）Ga（1-x）As薄膜 从x = 0到x = 0.53购买的GaAs/Si衬底。 InP或 InGaAs（P）将直接沉积在晶格上， 匹配In（53）Ga（47）As。 OEIC的绩效目标包括： 500 Mb/s数据速率、-40 dBm灵敏度和高效照明 检测范围为1.65微米。 在第一阶段，75微米平面 在GaAs/Si衬底上生长的InGaAs光电二极管将在 制造、寿命测试并作为原型沿着交付， 生长在硅衬底上的磷化铟外延层。 在第二阶段， 这些探测器将被组合在一个单一的芯片上， 双极晶体管，从而导致单片集成 接收机 探测器和接收器的设计和表征将 与S.R.教授一起完成。Forrest在部门 南加州大学的电子物理学教授。

Development of a fully monolithic integrated receiver chip for the 1.3 and 1.55 micron fibre optic wavelengths is proposed. The chip will be fabricated on a Si substrate so that conventional bipolar MOSFET technology can be used to construct all of the preamplifier electronics. We will use an innovative method for the growth of high-quality InP and related compound epitaxial layers on silicon substrates. The hydride VPE technique would be used to compositionally grade In(x)Ga(1-x)As films on a commercially purchased GaAs/Si substrate from x = 0 to x = 0.53. InP or InGaAs(P) would then be directly deposited onto the lattice- matched In(53)Ga(47)As. Performance goals of the OEIC include a 500 Mb/s data rate, -40 dBm sensitivity and efficient light detection out to 1.65 micron. During Phase I, 75 micron planar InGaAs photodiodes, grown on GaAs/Si substrates, will be fabricated, lifetested and delivered as prototypes along with an epitaxial layer of InP grown on a silicon substrate. In Phase II, these detectors will be combined on a single chip with a Si bipolar preamplifier, thus resulting in a monolithic integrated receiver. Detector and receiver design and characterization will be done in conjunction with Prof. S.R. Forrest in the Department of Electro Physics at the University of Southern California.