Distribution of VLSI Design Software for Education and Research

正在开发和改进匹兹堡大学研究项目中生产的计算机辅助设计工具，以便将其分发给普通用户。这些工具旨在帮助研究人员和教育工作者从VHDL语言描述中研究VLSI系统的综合。被增强的具体工具是：1)VComp，VHDL语言的子集的编译器，2)Vsim，相应的模拟器，3)为X11编写的伴随的原理图编辑程序，4)为X11编写的伴随的网表到原理图工具，5)“VF2VHDL”，从网表到VHDL语言的反向翻译器。任务包括：1)为编译器和模拟器生成文档，包括教程、示例和课堂助手；2)增强模拟器，以提供基于Stanford的IRSIM/Analyzer的图形波形显示包；3)将旧的原理图工具从Sunview转换为X11；4)清理用于分发的网表到X11的原理图工具；5)将网表更新为VHDL语言工具。将通过电子邮件提供技术支持。这项资助是在软件资本化计划下进行的。

CAD design tools, produced in research projects at the University of Pittsburgh are being developed and enhanced so as to bring them into a state for distribution to general users. These tools are designed to help researchers and educators investigate synthesis of VLSI systems from VHDL descriptions. Specific tools being enhanced are: 1) "Vcomp" a compiler for a subset of the VHDL language, 2) "Vsim" the corresponding simulator, 3) A companion schematic editor written for X11, 4) A companion netlist-to- schematic tool written for X11, 5) "VF2VHDL" a reverse translator from netlists to VHDL. Tasks include: 1) Generate documentation for the compiler and simulator with tutorials, examples, and classroom aides; 2) Enhance the simulator to provide a graphical waveform display package based on IRSIM/Analyzer from Stanford; 3) Convert the old schematic tool from sunview to X11; 4) Clean up for distribution the netlist to schematic tool for X11; 5) Update the netlist to VHDL tool. Technical support via email will be provided. This grant is made under the Software Capitalization Program.