PYI: Memory Systems for Cost-Effective Computer Architectures

这项研究的目标是开发具有成本效益的计算机体系结构，利用快速变化的技术。 这项工作的重点是内存系统，它必须为越来越快的处理器提供信息。 随着微处理器接近超级计算机的周期，存储器系统（包括I/O）成为个人计算机和大型机之间的主要区别。 目前的研究重点是开发新的技术来分析存储系统的性能。 一种新方法使用更新理论模型来提高时间采样跟踪驱动模拟的准确性。 该模型有望大幅减少模拟时间（10倍），而精度仅略有下降（小于10%）。 另一项新技术是缓存分析。 与传统的执行时间分析器类似，缓存分析器将程序的缓存性能与其源代码列表相关联。 程序员和编译器编写人员可以使用此信息来优化其程序的该高速缓存性能、重构代码和更改算法。 计算机架构师使用此工具来更好地理解缓存访问模式，从而改进缓存设计、同步机制和预取策略。

The goal of this research is to develop cost-effective computer architectures that take advantage of rapidly changing technologies. The thrust of this work is in memory systems, which must supply information to increasingly-faster processors. As microprocessors approach the cycle time of supercomputers, the memory system (including I/O) becomes the main difference between a personal computer and a mainframe. Current research focuses on developing new techniques for analyzing memory system performance. One new approach uses a renewal-theoretic model to improve the accuracy of time-sampled trace-driven simulations. This model promises to substantially reduce simulation time (10-fold) with only a small decrease in accuracy (less that 10%). Another new technique is cache profiling. Similar to traditional execution time profilers, a cache profiler relates a program's cache performance to its source listing. Programmers and compiler writers can use this information to optimize the cache performance of their programs, restructuring code and changing algorithms. Computer architects use this tool to better understand cache access patterns, leading to improved cache designs, synchronization mechanisms, and prefetch strategies.