ITR: Advanced Architectures and Technologies for Chip Multiprocessors

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Advanced Architectures and Technologies for Chip MultiprocessorsAbstractWe are poised on the verge of another discontinuity in computer performance as semiconductor technology enables Chip Multiprocessors (CMPs), wherein a single chip contains multiple processing elements connected via shared memory. These CMPs have the potential to greatly decrease the cost and increase the reliability of the information services that underpin society's essential infrastructure for commerce, science, education, and government.This research targets potential barriers to this paradigm shift with three thrusts:o Token coherence protocols to manage complexity. Token Coherence seeks to rebuild coherence on a new foundation that is more verifiable by (a) separating correctness from performance enhancements and (b) reducing correctness to a mechanism for safety (namely, tokens) and a mechanism for liveness and starvation freedom.o On-chip transmission lines to reduce on-chip communication latency. Conventional wires are limited by RC delay, which becomes a significant factor in deep-submicron semiconductor technologies. We will investigate using on-chip transmission lines to reduce latency and improve performance in CMPs.o Compressed caches to reduce off-chip bandwidth. CMPs must make effective use of limited off-chip bandwidth. We will investigate data compression techniques to both transfer fewer bits per cache block and increase effective on-chip cache size.