Integrated Framework for Test Synthesis, Power Optimization, and Reliable Design of VLSI Circuits

本研究是一种集成的方法来设计VLSI电路，重点是开发热应力和电应力测试，以及电源管理。第一个目标是使用压力测试作为一种低成本的替代方案。人们正在探索基于信号活度精确测量的电应力和热应力综合测试方法。在低功耗设计中，正在追求以下几点：1。在时序和DSP电路中开发基于蒙特卡罗的信号和故障活动估计方法；2. 寻找架构和系统级的功耗最小化技术；3. 研究用于电源管理的电流开关技术；和4。设计低功耗电路的布局算法。正在合成采样顺序和数字信号处理电路。

This research is an integrated approach to design of VLSI circuits, with an emphasis on developing tests for thermal and electrical stress, and power management. The first goal is to use stress testing as a low-cost alternative to burn-in. Methods to synthesize tests for electrical and thermal stress based on accurate measure of signal activity are being explored. In low power design, the following are being pursued: 1. develop Monte Carlo based approaches estimation of signal and glitching activity in sequential and DSP circuits; 2. find architectural and system-level power minimization techniques; 3. investigate current switching techniques for power management; and 4. design layout algorithms for circuits with low power consumption. Sample sequential and digital signal processing circuits are being synthesized.