Extent and Effects of Error Propagation and Recovery Mechanisms in Cache Memory Systems

商用微处理器系统正以越来越高的时钟速率工作。更快的时钟影响可用于从高速缓存存储器获取数据的时间，并且增加了高速缓存存储器系统中瞬时错误发生的概率。除了数据阅读错误之外，处理器子系统中也可能发生错误，并且它可能将错误的数据写入该高速缓存存储器中。 纠错码允许在码字限制内检测和恢复这些错误中的一些。快速错误检测允许损害遏制并减少恢复时间，否则恢复时间可能非常昂贵。本计画的目标是：（1）研究计算机系统中，当故障起源于处理器寄存器或高速缓存位置时，由于瞬时故障而引起的错误传播的程度;（2）开发所需的技术和硬件支持，以便在低开销和低性能损失的计算任务中早期检测和从这种错误中恢复。所提出的技术将涵盖从仅检测到完全错误恢复的广泛范围。这项研究将确定的架构功能，在商业微处理器中提供时，将使它们适用于容错应用。 目的是将正常操作中的性能影响保持在最低限度。

Commercial microprocessor systems are being operated at higher and higher clock rates. Faster clocks impact the time that is available to fetch data from cache memory, and increases the probability of transient error occurrence in cache memory systems. Besides data reading error, an error may also occur in the processor subsystem, and it may write erroneous data into the cache memory. Error-correcting codes allow detection and recovery from some of these errors within the code word limits. Fast error detection allows damage containment and reduces the recovery time, which otherwise could be very expensive in time. The goals of this project are: (1) to study the extent of error propagation due to transient faults in computer system when a fault originates either in a processor register or a cache location; and (2) to develop techniques and hardware support needed for early detection and recovery from such errors in computation tasks with low overhead and low performance loss. The proposed techniques will cover a broad spectrum from only detection to full error recovery. This research will identify architectural features which, when provided in commercial microprocessors, will make them suitable for use in fault-tolerant applications. The intent is to keep the performance impact in the normal operation to a minimal.