Testing of High-Density VLSI Random-Access Memories

本课题研究的是先进技术芯片内嵌存储器中工艺参数故障的检测方法。阈值电压变化和噪声（例如，泄漏、电荷共享、串扰等）对存储单元功能的影响（使用电路仿真和分析）根据读/写误差范围和访问延迟方差进行建模。基于过程和电路研究产生的故障模型的存储器故障模式算法正在开发中。基于它们的工具允许对静态ram进行功能和参数测试。从算法的角度分析了具有多值地址解码方案的千兆可伸缩dram的测试问题。与这些类似模拟的组件相关的故障模型和内存测试算法正在被探索。一种用于测试高密度sram和多值可拉伸dram的混合模式电路的方法，使用纯正弦输入信号的谐波失真测量，以提取存储芯片中各种技术，参数和布局相关故障的检测和诊断信息。

This research is on test methods for finding process parameter faults in memories embedded in advanced technology chips. The effect of threshold voltage variation and noise (e.g., leakage, charge sharing, crosstalk, etc.) on the functionality of a memory cell is modeled (using circuit simulation and analysis) in terms of read/write error margins and variance of access delays. Algorithms for failure modes in memories, based on fault models generated from process and circuit studies, are being developed. Tools based on them allow functional and parametric testing of static RAMs. The issues of testing gigabit stretchable DRAMs with multi-valued address decoding schemes are being analyzed from an algorithmic standpoint. Fault models, pertaining to these analog-like components, and memory testing algorithms are being explored. One methodology for testing high-density SRAMs and multivalued stretchable DRAMs with mixed-mode circuits, uses the measure of the harmonic distortion of a pure sinusoidal input signal in order to extract detection and diagnosis information for various technology, parametric and layout-related faults in the memory chip.