Sub-Threshold Digital Logic

超低功耗数字逻辑设计可以通过工作在亚阈值区域的晶体管来实现。该器件模拟了几乎整个VDS范围内的理想恒流源。对于串联的晶体管，每个晶体管上的VDS降可以忽略不计，这允许实现大型复杂的门。亚阈值区域的设计可以细分为器件和电路问题。在设备层面，正在调查扩展问题。在电路级，正在研究基于各种逻辑族(例如，CMOS、伪NMOS、源极耦合逻辑和差分电流开关逻辑)的电路设计的稳健性、性能-功耗权衡和适用性。正在设计几个逻辑系列，专门用于亚阈值区域。正在与其他低功耗设计技术，如绝热准静态cmos逻辑进行比较。正在探索噪声分析的方法，包括闪烁和热噪声。

Ultra low power digital logic design can be achieved by operating transistors in the sub-threshold region. The device mimics and ideal constant current source for almost the whole VDS range. For serially connected transistors, the VDS drop on each transistor is negligible, which allows the implementation of large complex gates. The design in the sub-threshold region can be subdivided into device and circuit issues. At the device level, scaling issues are being investigated. At the circuit level, robustness, performance-power trade-offs and the applicability of circuit design based on various logic families (e.g. CMOS, Pseudo-NMOS, Source Coupled Logic, and Differential Current Switch Logic) are being studied. Several logic families are being designed to work specifically in the sub-threshold region. Comparisons with other low power design techniques, e.g. adiabatic Quasii-Static CMOS logic, are being made. Methods for noise analysis, including flicker and thermal noised, are being explored.