Wafer Oriented Trend Analysis for VLSI Test Opitmazation

提高IC测试质量的主流方法是开发更好的测试，以更真实的故障机制为目标。 该项目正在研究一种正交方法，该方法通过采用基于晶圆的空间测试信息作为解释测试结果的额外输入，可以显著提高任何给定测试程序的有效性。 由于广泛观察到的半导体晶片上的缺陷聚集以及电路参数紧密跟踪同一晶片上的相邻管芯的事实，该空间信息在对电路质量做出最佳可能判断时是有用的。 早期的结果表明，潜在的缺陷水平的改善高达一个数量级的筛选高品质的电路，并筛选出潜在的早期寿命故障的可能性，而无需昂贵的老化测试。 正在进行的研究旨在验证新的，更大量的，工业测试数据的这些发现，并开发分析模型来估计测试质量的改进。 这种新方法也正在研究开发基于邻域的阈值，用于最佳地解释非布尔测试方法（如IDDQ和极低电压测试）中的测试结果。

The mainstream approach to improving the quality of IC testing is to develop better tests that target more realistic failure mechanisms. This project is investigating an orthogonal approach that promises significant improvements in the effectiveness of any given testing procedure by employing wafer based spatial test information as additional input in interpreting test results. This spatial information is useful in making the best possible judgement about circuit quality because of the widely observed clustering of defects on semiconductor wafers, and the fact that circuit parameters track closely for adjacent dice on the same wafer. Early results indicate the potential for defect level improvements up to an order of magnitude in screening for high quality circuits, and the possibility of screening out potential early-life failures, without expensive burn-in tests. On-going research aims at validating these findings on new, more voluminous, industrial test data, and also developing analytical models to estimate the test quality improvements. The new approach is also being investigated for developing neighborhood-based thresholds for optimally interpreting test results in non-Boolean test approaches, such as IDDQ and very low voltage testing.