Towards enabling a 2-3 orders of magnitude improvement in call handling capacities of switches

对于构建大规模交换机，目前业界关注的焦点是将交换结构的分组处理能力从Gb/s提高到Tb/s。虽然分组处理能力和线卡数据速率的增加要求交换机的呼叫处理能力相应增加，但这个问题很少受到关注。这是因为大多数关于分组交换结构可扩展性的工作都针对无连接的互联网协议（IP）路由器，而呼叫处理仅在面向连接的网络中出现。然而，在过去的几年中，支持服务质量（QoS）保证流的资源预留引起了人们的关注。互联网工程任务组（IETF）正在通过增加IP路由器的面向连接功能来解决这个问题。在面向连接的网络中，用于建立和释放连接的信令协议影响其呼叫处理能力。信令消息可能很复杂，有许多参数和计时器，并且与调用相关的状态信息可能变得笨拙。因此，信令协议传统上是在软件中实现的。QoS控制解决方案的开发和评估是基于呼叫处理能力不能随交换结构的分组处理能力而扩展的前提。这种关于呼叫处理能力的假设也将电路交换网络（包括高速波分复用网络）降级为仅仅充当电线。该提案通过展示数百万个呼叫/秒的呼叫处理能力来挑战这一基本假设。改变这个关于呼叫处理能力的基本假设确实会对分组交换网络的QoS控制机制和新兴高速电路交换网络用于具有挑战性的新应用的使用产生深远的影响。我们的解决方法是在可重构的现场可编程门阵列（FPGA）硬件中实现信令协议。fpga可以随着信令协议的发展而重新编程，同时显著提高相对于软件实现的呼叫处理能力。为了管理复杂性，我们建议在硬件上实现协议的基本和经常使用的操作，并将复杂和不常用的操作降级到软件中。与无状态协议相比，信令协议维护每个呼叫的状态信息。为了管理相关的内存需求，我们建议只维护硬件中每个调用的基本状态信息。在这个项目中，我们建议(i)在fpga中实现一个典型的信令协议，（ii）使用信令协议fpga设计一个开关控制器板，以及（iii）量化实现的措施，以展示可实现的呼叫处理能力。

Toward building large-scale switches, the current industry focus is on increasing packet handlingcapacities of switch fabrics from Gb/s to Tb/s. Although an increase in packet handlingcapacities and line card data rates requires a corresponding increase in call handling capacities ofswitches, this problem has received little attention. This is because most of the work on scalabilityof packet switch fabrics has targeted connectionless internet protocol (IP) routers, while call handlingarises only in connection-oriented networks. However, in the last few years, resource reservationto support Quality-of-Service (QoS) guaranteed flows has gained attention. InternetEngineering Task Force (IETF) is addressing this issue by augmenting IP routers with connection-orientedcapabilities. In a connection-oriented network, the signaling protocol that is used to set up and release connectionsimpacts its call handling capacity. Signaling messages can be complex with many parametersand timers and the state information associated with calls can become unwieldy.Consequently, signaling protocols have traditionally been implemented in software. QoS controlsolutions are being developed and evaluated based on the premise that call handling capacities donot scale with the packet handling capacities of switch fabrics. This assumption regarding callhandling capacities has also relegated circuit-switched networks, including high-speed Wave-lengthDivision Multiplexed networks, to just serve as wires. This proposal challenges this basicassumption by demonstrating call handling capacities in the order of millions of calls/sec. Changingthis basic assumption regarding call handling capacities would indeed have a far-reachingimpact on both QoS control mechanisms for packet-switched networks, and on the use of emerginghigh-speed circuit-switched networks for challenging new applications. Our solution approach is to implement signaling protocols in reconfigurable Field ProgrammableGate Array (FPGA) hardware. FPGAs can be reprogrammed as signaling protocols evolvewhile significantly improving the call handling capacities relative to software implementation. Tomanage complexity, we propose to implement the basic and frequently-used operations of the protocolin hardware, and relegate the complex and infrequently-used operations to software. In contrastto stateless protocols, signaling protocols maintain state information for each call. Tomanage associated memory requirements, we propose to maintain only the essential state informationfor each call in hardware. In this project we propose to (i) implement a typical signalingprotocol in FPGAs, (ii) design a switch controller board using the signaling protocol FPGAs, and(iii) quantify measures of the implementation to demonstrate achievable call handling capacities.