Efficient and Performance Guaranteed Methods for Order Reduction and Analysis of VLSI Interconnect Circuits

高速深亚微米VLSI技术的发展要求芯片互连和封装采用分布式电路建模。如此详细的建模水平最终导致需要分析的大规模线性电路。因此，本课题的研究目标是开发一种新的电路降阶方法，以在合理的时间周期内，在保证电路性能的前提下，对电路的性能和特性进行评估。本课题的主要任务是：a)开发新的降阶方法，提供有保证的性能；b)推导相应的高效数值方法；c)研究降阶系统中保持优先特性的方法及其实现问题；d)研究小波方法在模型降阶和分析中的应用；为UT-Dallas和UNC-Charlotte的研究生教育做出贡献。预期的研究成果将为VLSI互连电路的降阶和分析提供有效和性能保证的方法，以及相应的算法和仿真测试软件。它还将通过提供预期的研究成果和软件，为工程和科学方面作出贡献，并为研究生教育作出贡献。

The advance of high-speed deep-submicron VLSI technology requires chipinterconnect and packaging to be modeled by distributed circuits. Such adetailed modeling level eventually results in large scale linear circuits tobe analyzed. Thus, the research objective is to develop new circuit orderreduction approach to evaluate the circuit performance and characteristicsin a reasonable time period and with a guaranteed performance, as requiredby real design practice.This project focuses on the following tasks:a) Develop new order reduction approaches that provide guaranteed performance;b) Derive correspondingly high efficiency numerical methods;c) Investigate the methods of maintaining preferred characteristics in thereduced order system as well as related implementation issues;d) Investigate wavelet method application in model order reduction andanalysis; ande) Contribute to graduate education at UT- Dallas and UNC-Charlotte.The expected research results will provide efficient and performanceguaranteed methods for order reduction and analysis of VLSI interconnectcircuits, and their corresponding algorithms and software for simulationtest. It will also contribute to engineering and science aspects by theexpected research results and software, as well as to graduate education.