Improving System Functionality using Monitoring Processors

微处理器现在在原始处理能力上与超级计算机竞争，这要归功于晶体管密度的增加和架构上的进步，比如并行性的利用。然而，内存系统的带宽和延迟是如此有限，以至于微处理器性能的提高往往导致很少的整体系统改进。与此同时，软件成本也在迅速增长。本研究探讨了使用一些不断增加的硅空间来提供额外的功能。该方法是将这些新晶体管的一部分用于提供可编程监控硬件，以增强软件开发，提高调试效率，提高可靠性并提供运行时安全性。在监视嵌入式系统的运行时保证和不变量方面还可以找到其他应用程序。举一个具体的例子，这种方法可以解决软件中出现的与指针相关的缺陷，这些缺陷使系统不可靠，容易受到黑客的攻击。一个简单的辅助协处理器通过松耦合（例如通过L1缓存一致性总线）监视来自计算处理器的地址引用。这种松耦合降低了设计复杂性，避免了重新设计任何核心CPU的需要，并允许将这种方法轻松添加到现有设计中。此外，该方法是对静态编译器分析技术的补充，该研究扩展了传统的分析，以开发有效的运行时监控功能。

ABSTRACTProposal #0113418U of Cal DavisFarrens, MatthewMicroprocessors now rival supercomputers in raw processing power, thanks to increases in transistor densities and architectural advances such as the exploitation of parallelism. However, the bandwidth and latency of memory systems is so limited that increasing performance in the microprocessor often leads to little overall system improvement.At the same time that this is occurring, software costs are burgeoning. This research explores using some of the increasing silicon real estate to provide extra functionality. The approach is to dedicate a portion of these new transistors to provide programmable monitoring hardware to enhance software development, make debugging more efficient, increase reliability and provide run-time security. Additional applications may be found in monitoring run-time guarantees and invariants for embedded systems.Taking a specific example, this approach can address pointer-related defects occurring in software which render systems unreliable and vulnerable to hackers. A simple, auxiliary co-processor monitors address references from a compute processor via a loose coupling (e.g. via the L1 cache coherence bus). This loose coupling reduces design complexity and avoids the need for any core CPU redesign and allows this approach to be readily added to existing designs. Furthermore, the approach is complementary to static compiler analysis techniques and the research extends conventional analysis to exploit efficient run-time monitoring capabilities.