High-Bandwidth Memory Pipeline for Wide-Issue Processors

摘要建议：0073259 PI：Gyunho Lee职务：技术和体系结构的创新使得功能强大的微处理器能够以非常高的时钟速率同时发出多条指令。在未来的处理器与积极的投机技术，甚至更大的数量的指令问题，每个周期的预期。有效地处理用于数据访问的存储器引用是在未来处理器中实现高性能的关键之一。本研究旨在提供足够的带宽，在快速延迟的数据访问宽问题处理器发出数十个指令，每个周期的方法。这些方法是基于“数据解耦”的概念。数据解耦将存储器引用指令划分为多个独立的流，然后才知道它们访问的数据的实际地址。分区的存储器引用指令然后被馈送到单独的存储器流水线中。本研究探讨在多记忆体管线的基础上，以资料解耦合为基础，在有效且有效率的硬体与软体支援上的问题。提供多个存储器流水线的数据解耦方法可以提供优于常规设计的两个关键优点。首先，降低了构建具有许多端口的大型高速缓存的成本和复杂性。第二，划分存储器引用可以促进对每个划分的流的更专门的处理。

ABSTRACTProposal: 0073259PI: Gyungho LeeTitle: High-Bandwidth Memory Pipeline for Wide-Issue Processors Technological and architectural innovations have enabled development of powerful microprocessors that can issue several instructions concurrently at a very high clock rate. In future processors with aggressive speculation techniques, an even larger number of instruction issues per cycle are expected. Efficient handling of memory references for data access is one of the keys to achieving high performance in future processors. This research addresses methods to provide sufficient bandwidth at fast latency for data access in wide-issue processors issuing tens of instructions per cycle. The methods are based on the concept of "data decoupling". Data decoupling divides the memory reference instructions into multiple independent streams before the actual addresses of the data they access are known. Partitioned memory reference instructions are then fed into a separate memory pipeline. This research investigates the issues in effective and efficient hardware and software support for multiple memory pipelines based on data decoupling. The data decoupling approach of providing multiple memory pipelines can provide two crucial advantages over a conventional design. First, the cost and the complexity of building a large cache with many ports are reduced. Second, partitioning memory references can facilitate more specialized handling of each partitioned stream.