Combining Hardware and Software Monitoring for Improved Power and Performance Tuning
Combining Hardware and Software Monitoring for Improved Power and Performance Tuning
批准号:
0311180
负责人:
Ruth Bahar
金额:
$16.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2003
资助国家:
美国
项目状态:
已结题
起止时间:
2003-08-15 至 2007-07-31
中文摘要
结合硬件和软件监控以改进功耗和性能调优摘要动态配置处理器资源以匹配程序的需求已被证明是在不牺牲性能的情况下降低CPU功耗的有效方法。本研究的重点是结合软件分析和硬件监控技术来驱动重新配置过程。所提出的方法基于这样一个前提,即每种方法都有不同的优点和缺点,它们的组合将更好地预测应用程序的动态行为。使用这些信息,处理器的某些部分可以以较低的功耗运行,或者在不需要时完全关闭,并在需要之前上电。我们将探讨降低功耗的三种方法:(1)取暂停,(2)取消激活选择执行指令的部分逻辑和部分问题队列,以及(3)取消激活一些ALU。这三个组件是相互关联的,因为取暂停可以减少准备发出的指令的数量,这可能导致一些功能单元变得空闲。此外,不停止获取单元可能会导致问题队列填满,并延迟关闭队列条目。这项研究的目标是找到结合软件和硬件技术的有效方法,以显着降低一系列架构的能耗,这些架构可能包括多线程和芯片上的多个处理器等功能。
英文摘要
BaharCombining Hardware and Software Monitoring for Improved Power and Performance TuningAbstractDynamically configuring processor resources to match a program's needs has been shown to be an effective means of reducing CPU power dissipation without sacrificing performance. This research focuses on combining software profiling and hardware monitoring techniques to drive the reconfiguration process. The proposed approach is based on the premise that each has different strengths and weaknesses and their combination will give a better prediction of the dynamic behavior of an application. Using this information, parts of the processor can be run at reduced power or shut down completely when they are not needed and powered up just before they are.Three methods that will be explored for reducing power are: (1) fetch halting, (2) deactivating parts of the logic that select instructions for execution and parts of the issue queue, and (3) deactivating some of the ALU's. The three components are interrelated because fetch halting can decrease the number of instructions that become ready to issue, which can cause some of the functional units to become idle. In addition, not halting the fetch unit can cause the issue queue to fill up and delay turning off queue entries. The goal of this research is to find effective ways of combining software and hardware techniques to significantly lower energy consumption over a range of architectures that may include features such as multithreading and multiple processors on a chip.
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