ITR: Post-Silicon Validation and Diagnosis Based Upon Statistical Delay Models

随着制造技术向纳米范围发展，主要挑战之一是确保设计的预期行为与其在真正硅芯片中的实际行为之间的一致性。由于深亚微米(DSM)效应，如工艺变化、小缺陷和电噪声，在设计投入生产之前预测设计在硅上的时序行为或保证这种时序行为变得越来越困难。为了避免制造放缓，该行业需要新型的硅后验证和诊断工具，这些工具将有效地解决设计模型与其在硅芯片上的实现之间的不一致。为了迎接这一挑战，PI提出了新的统计方法，将更好地模拟和更准确地模拟设备的时序行为。PIS在这个项目中提出了三个研究组成部分，以与他们计划的教育活动相结合：(1)定时问题的诊断，(2)硅后验证和调试，以及(3)定时质量的预测。在诊断方面，将开发技术来定位故障芯片上的时序问题，确定这些问题是否可能是由于制造缺陷造成的。在验证和调试中，将开发技术以确保用于设计芯片的模型的时序行为与制造过程中观察到的时序行为之间的一致性。对于第三个组成部分，计时质量的预测，将开发技术来对批量生产阶段的计时质量水平进行统计推断。拟议的研究将通过将分析带到更抽象的水平来补充DSM电路和工艺变化的建模方面的其他研究工作。与直接处理晶体管和电线不同，这些工具将对相关的随机变量进行操作，这些变量对晶体管和电线的计时行为进行建模。该项目将促进开发用于大型和复杂设计的实用工具。当提出的统计工具和方法可用时，芯片设计者可以放松各种参数的度量，以获得最佳的设计权衡，从而将制造技术推向尖端。当硅的计时问题能够被更有效地检测和更好地理解时，公司就可以避免在与制造不确定性作斗争时浪费资源，并将这些资源用于更具生产力的用途。

As the manufacturing technologies move toward nanometer ranges, one of the major challenges is to ensure consistency between the behavior expected of a design and its actual behavior in a real silicon chip. Due to Deep Sub-Micron (DSM) effects such as process variations, small defects, and electrical noise, it has become increasingly difficult to predict the design's timing behavior on silicon, or to guarantee such timing behavior before the design goes into production. To avoid slowdowns in manufacturing, the industry needs novel post-silicon validation and diagnosis tools that will effectively resolve the inconsistency between a design model and its implementation on a silicon chip. To meet the challenge, the PIs propose novel statistical approaches that will better model, and more accurately simulate, the timing behavior of a device. The PIs propose three research components in this project to be integrated with their planned educational activities: (1) diagnosis of timing problems, (2) post-silicon validation and debugging, and (3) prediction of timing quality. In diagnosis, techniques will be developed to locate timing problems on faulty chips, determining whether these problems may be due to manufacturing defects. In validation and debugging, techniques will be developed to ensure consistency between the timing behavior of models used to design a chip and that which is observed during the manufacturing process. For the third component, prediction of timing quality, techniques will be developed to draw statistical inference about the timing quality level in the stages of mass production. The proposed research will complement other research efforts in the modeling of DSM circuits and process variations by taking the analysis to a more abstract level. Rather than dealing directly with transistors and wires, the proposed tools will operate on correlated random variables that model the timing behavior of transistors and wires. This project will facilitate the development of practical tools for large and complex designs. When the proposed statistical tools and methodologies become available, chip designers can relax the metrics of various parameters in order to obtain the best design tradeoff, thus pushing manufacturing technologies to the cutting edge. When silicon's timing problems can be more effectively detected and better understood, companies can avoid wasting resources in struggling with manufacturing uncertainties and devote these resources to more productive uses.