SHF: Small: Design-for-Debug Architecture for Post-Silicon Security Validation

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System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems, starting from simple electronic devices in smart homes to complex navigation systems in airplanes. SoCs are designed today using hardware components, often gathered from untrusted third-party vendors, to meet cost and time-to-market constraints. These hardware components may have vulnerabilities, which an attacker can exploit to leak secret information or cause system malfunction. While researchers have proposed many promising ideas to detect pre-silicon vulnerabilities, the existing solutions are not useful for fabricated chips (referred to as "post-silicon" stage), since it is not possible to observe or analyze all the internal signals. Moreover, it is infeasible to detect a wide variety of vulnerabilities during fabrication and/or validation (at the "pre-silicon" stages) due to runtime and other constraints. Post-silicon security validation will enable secure and trustworthy systems. The impacts of this project are to develop highly secure SoCs through synergistic integration of pre-silicon verification with post-silicon security validation, working closely with industry to enable technology transfer and produce results with practical significance, and training students of diverse backgrounds for the workforce.The primary objective of the proposed project is to develop automated tools and techniques to detect post-silicon security vulnerabilities using an effective combination of simulation-based security validation and side-channel analysis. Specifically, the project will develop a comprehensive list of SoC vulnerabilities, and design a fully automated and cost-effective mechanism for monitoring of runtime security threats. In order to improve the observability in fabricated chips, the project will develop an effective design-for-debug architecture. The project will also utilize side-channel analysis for vulnerability detection. A successful implementation of this project is expected to drastically reduce the overall SoC security validation effort.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.