MRI: Acquisition Of a TLP Testing Cluster for Advanced ULSI On-Chip ESD Protection Research Down to Nanoscale and Advanced RF/Mixed Signal ICs

PI要求NSF-MRI基金收购并建立一个TLP（传输线脉冲）测试系统集群，用于研究ULSI IC（低至纳米级）和高级RF/混合信号IC的片上ESD（静电放电）保护。机构成本分担率为43%。知识优势：随着半导体技术进入超深亚微米（VDSM）ULSI（超大规模集成电路）领域，ESD故障成为集成电路（IC）可靠性的主要问题。需要片上ESD保护电路来保护IC芯片免受ESD损坏。目前，在ESD保护电路设计实践中，试错法仍然占主导地位。我将协助首席研究员进行其目前的研究，而首席研究员的研究小组正积极研究用于无线和信息处理应用的先进射频/混合信号集成电路，包括多模式/频段通用数字射频片上系统（SoC）和高性能低功耗模数转换（ADC）集成电路。由4002型动态TLP测试仪和精密热/冷8la晶片探针、频谱/网络分析仪、半导体参数分析仪、低噪声超GHz RF探针台和噪声分析仪组成的TLP测试系统集群对这些研究活动的成功起着至关重要的作用。因为它允许在超GHz频谱和超快亚GHz频谱中对ESD保护器件和RF/混合信号IC进行精确的静态/瞬态非破坏性表征，更广泛的影响：该TLP测试系统集群将显著增强IIT的研究和教学基础设施，通过在IIT进行先进的ESD保护、RF和混合信号IC SoC研究，实现研究和教育的整合&。将利用这种仪器开发几门新课程和实验室。建议使用该集群将多样性融入IIT的研究和教学。该设施是中西部地区唯一的此类设施，将向跨学科研究活动和外部用户开放，以促进ESD保护、RF/混合信号IC和其他更广泛的微电子研究方面的跨学科和大学-产业合作。

The PI requests NSF-MRI funds to acquire and establish a TLP (transmission-line-pulsing) Testing System Cluster for research on on-chip ESD (electrostatic discharge) protection for ULSI ICs down to nano-scale and advanced RF/mixed-signal ICs. Institutional cost sharing is 43%.Intellectual Merits: ESD failure becomes a major integrated circuit (IC) reliability problem as semiconductor technologies move into the very-deep-sub-micron (VDSM) ULSI (ultra large- scale integration) regime. On-chip ESD protection circuitry is required to protect IC chips against ESD damage. Currently, trial-and-error approaches still dominate in ESD protection circuit design practice. I will help the PI in his current research as well as the PI's group is pursuing active research on advanced RF/mixed-signal ICs for wireless and information processing applications under different sponsorship, including multi-mode/band universal digital RF systems-on-a-chip (SoC) and high-performance low-power analog-to-digital conversion (ADC) ICs. A TLP Testing System Cluster, consisting of Model 4002 Dynamic TLP Tester and precision heat/cold 8la wafer probe, spectrum/network analyzers, semiconductor parametric analyzer, low-noise super-GHz RF probe station and noise analyzer, plays a critical role to the success of these research activities, because it allows accurate static/transient non-destructive characterizing ESD protection devices and RF/mixed-signal ICs in super-GHz spectrum and ultra-fast sub-1ns time domain, which is particularly critical to sub-100nm/nano-scale/super-RF ESD protection.Broader Impacts: This TLP Testing System Cluster will significantly enhance the research and teaching infrastructure at IIT that enables integrating research and education via performing advanced ESD protection, RF and mixed-signal IC & SoC research at IIT. Several new courses and laboratories will be developed using this instrumentation. Integrating diversity into research and teaching at IIT using this Cluster is proposed. The facility, the only one of the kind in the Midwest region, will be open to inter-disciplinary research activities and external users to promote cross-disciplinary and university-industry collaboration on ESD protection, RF/mixed- signal ICs and other broader microelectronics research.