CAREER: Interconnect-Centric Layout Synthesis and Planning with Consideration of On-Chip Inductance

本研究是一个以互连线为中心的版图设计方法，将片上电感的方法。具体而言，以下问题进行了探讨：（1）多个耦合RLC互连的精确建模和分析技术：（2）有效的互连综合算法，以优化性能和信号完整性的耦合RLC网络;（3）考虑到互连优化技术的综合集合的用于预布局互连估计的有效算法，以及将估计结果应用于互连结构规划;以及（4）用于功能块的最大开关电流的预布局估计的有效算法，随后使用RLC模型优化电源结构。此外，该项目还研究了一个创新的计算机工程课程，将互连和片上系统（SOC）的考虑，并开发基于Web的互连规划工具，用于创新教学和校园外的推广。

This research is on an interconnect-centric layout design methodology incorporating on-chip inductance into the methodology. Specifically, the following problems are explored: (1) accurate modeling and analysis techniques for multiple coupled RLC interconnects; (2) efficient algorithms for interconnect synthesis to optimize performance and signal integrity for coupled RLC nets; (3) efficient algorithms for pre-layout interconnect estimation considering a comprehensive set of interconnect optimization techniques, and application of estimation results to interconnect architecture planning; and (4) efficient algorithms for pre-layout estimation of maximum switching current for functional blocks followed by optimization of the power supply structure using the RLC model. In addition, this project investigates an innovative computer engineering curriculum incorporating interconnect and System-On-Chip (SOC) considerations, and development of Web-based interconnect planning tools for use in innovative teaching and for outreach beyond the campus.