Interconnect Planning in Placement and Logic Synthesis

提案编号：0427821INSTUTION：加州大学圣巴巴拉分校PRINCIPAL研究员：Marek-Sadowska，MalgorzataTITLE：布局和逻辑综合中的互连规划摘要：由于技术的巨大进步，VLSI芯片变得非常大和复杂，这一趋势预计将继续下去。芯片复杂性的增加导致平均互连线长度增加，互连线所占芯片面积的比例越来越大。这一趋势不仅是由于设计复杂性的增加，也是因为现有的CAD工具不能很好地扩展。该方案在比布线更高的设计抽象中解决了与亚微米技术中的互连相关的几个问题。在设计流程中，布局是在很大程度上决定互连特性的一个步骤。其意图是将几个目标集成到布局中，这些目标通常是通过放置(通常是布线)设计上的点工具来解决的。我们的目标是开发一种高效的、多目标的增量配置器，能够提供众所周知的权衡。除了布局级的增量修正外，还将研究和开发集成到布局流程中的电路优化方法。定时驱动的布局流程将集成重定时、顺序预算、偏斜优化和同步全局布线。预计布局一级的工作将产生有效的优化技术，并将有助于制定更高级别工具的要求，以创建更容易的可布线设计。

PROPOSAL NO: 0427821INSTITUTION: University of California-Santa BarbaraPRINCIPAL INVESTIGATOR: Marek-Sadowska, MalgorzataTITLE: Interconnect Planning in Placement and Logic SynthesisAbstract:Due to the tremendous progress in technology, VLSI chips become very large and complex, and this trend is expected to continue. The increased chip complexity causes that average interconnect lengths increase and proportionally larger and larger fraction of chip's area is occupied by interconnects. This tendency is not only caused by the increased design complexities, but also by the fact that the existing CAD tools do not scale well. This proposal addresses several issues related to interconnects in submicron technologies at design abstractions higher than routing. In design flow, placement is a step which to a large extent, determines the interconnect characteristics. The intension is to integrate into placement several objectives, which are conventionally solved by point tools on placed (and often on routed) designs. The goal is to develop an efficient, multi-objective incremental placer capable of offering well-understood tradeoffs. Besides incremental corrections at the placement level, methodologies of circuit optimization integrated into placement flow will be studied and developed. Timing-driven placement flow will integrate retiming, sequential budgeting, skew optimization, and simultaneous global routing. It is expected that the work at the placement level will result in efficient optimization techniques and will help in formulating requirements for the higher level toolsto create easier routable designs.