SHF: Small: Modeling and Preventing Electromigration-Caused Degradation in Cu Dual Damascene Scaled Interconnects

SHF：小型：建模并防止铜双镶嵌互连中电迁移引起的退化

• 批准号: 1115663
• 负责人: Malgorzata Marek-Sadowska
• 金额: $ 35万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1115663&HistoricalAwards=false
• 关键词: SHF; Small; Modeling; Preventing; Electromigration

Modern computer chips contain billions of tiny transistors connected by wires. The massively integrated circuits (ICs) are prone to wear out and degradation during their lifetimes. When electric current flows in a microscopic wire, the moving electrons collide into diffusing metal atoms and cause a gradual ion movement. This current-flow-induced material transport is called electromigration (EM). The electromigration phenomenon is a major source of interconnect degradation. Over time EM may cause wire breaks or shorts leading to circuit malfunction. Greater current densities, wire geometry or material imperfections, and increased temperature worsen EM. In the past, improvements in interconnect manufacturing kept pace with interconnect scaling and allowed for relatively simple ways of keeping EM at bay by capping current densities. Interconnect scaling is now approaching the point where the existing models and assumptions are no longer valid. At the same time chip?s thermal conductivity decreases while the density of currents carried by the on-chip wires and the operating power steadily increase causing significant self-heating. These effects bring again EM to the forefront and cause that it now poses a serious reliability threat for working chips. There is an urgent need to develop a comprehensive chip-level EM analysis tool. The PI proposes to develop a physical EM simulator to understand failure mechanisms in various interconnect configurations. The PI will use the simulator to develop metrics for wire time-to-failure estimates. The PI proposes to develop statistical models of interconnect failure and a chip-level analyzer of electromigration degradation effects. Interconnects whose expected lifetimes are shorter than desired can be modified. The will develop such modification strategies as well.This work supports the US semiconductor industry by addressing a vital research problem that may affect the integrated circuits scaling trends. The proposed techniques would be useful for designers because the worst circuit degradation conditions occur in small regions of the chip that can be identified and resolved. In addition, the tools to be developed may also help process engineers to study the effects of new materials on circuit level properties. The proposed research activities will also serve as a platform for training PhD students who will be well prepared to work in modern industry or academia.

现代计算机芯片包含数十亿个通过导线连接的微小晶体管。大规模集成电路（IC）在其寿命期间易于磨损和退化。当电流在微观导线中流动时，移动的电子碰撞扩散的金属原子，并引起逐渐的离子运动。这种电流引起的材料传输称为电迁移（EM）。 电迁移现象是互连退化的主要来源。随着时间的推移，EM可能会导致电线断裂或短路，从而导致电路故障。更大的电流密度、导线几何形状或材料缺陷以及温度升高会使EM恶化。在过去，互连制造的改进与互连缩放保持同步，并且允许通过限制电流密度来保持EM在海湾的相对简单的方式。互连扩展现在正在接近现有模型和假设不再有效的点。与此同时，芯片？的热导率降低，而芯片上的导线所携带的电流密度和工作功率稳定地增加，从而导致显著的自加热。这些影响再次将EM带到了最前沿，并导致它现在对工作芯片构成了严重的可靠性威胁。迫切需要开发一种全面的芯片级EM分析工具。PI建议开发一个物理EM模拟器，以了解各种互连配置中的故障机制。PI将使用模拟器开发导丝失效时间估计的指标。PI建议开发互连故障的统计模型和电迁移退化效应的芯片级分析仪。可以修改预期寿命短于期望寿命的互连。这项工作通过解决可能影响集成电路缩放趋势的重要研究问题来支持美国半导体行业。所提出的技术将是有用的设计，因为最坏的电路退化条件发生在芯片的小区域，可以识别和解决。此外，待开发的工具还可以帮助工艺工程师研究新材料对电路级性能的影响。拟议的研究活动还将作为培养博士生的平台，这些博士生将为在现代工业或学术界工作做好充分准备。