Research on Layout and Logic Design

提出的研究方向是布局驱动综合，即逻辑综合与物理设计的交叉。重点研究合成数字系统中逻辑网络的重构问题。目前正在研究四个主题，以提高路由效率或功耗。它们是：1)增量逻辑重新合成以控制布线，2)耦合布线与逻辑重构，并找到优化以消除布线溢出。3)使用广义Reed-Muller形式来分析逻辑，以帮助设计单元库和技术映射，开发新的多层优化技术，设计可证明具有良好可测试性的网络。4)在逻辑综合的技术独立和技术依赖层面，开发新的功率优化方法，并找到更好的路由工具来处理功率约束。

The proposed research is on layout driven synthesis, i.e. the intersection of logic synthesis and physical design. The focus is on restructuring logic networks in synthesized digital systems. Four topics, which meet the goals of improving routing efficiency or power consumption, are being investigated. These are: 1) Incremental logic resynthesis to control wiring, 2) Coupling wiring with logic restructuring and finding optimizations to eliminate wiring overflows. 3) Use of generalized Reed-Muller forms to analyze logic as an aid to: - designing cell libraries and for technology mapping, - developing new multi level optimization techniques, - designing networks of provably good testability. 4) Develop new methods for power optimization, at the technology independent and technology dependent levels in logic synthesis, and also find better routing tools to handle power constraints.