Research on Layout and Logic Design

布局与逻辑设计研究

基本信息

项目摘要

The proposed research is on layout driven synthesis, i.e. the intersection of logic synthesis and physical design. The focus is on restructuring logic networks in synthesized digital systems. Four topics, which meet the goals of improving routing efficiency or power consumption, are being investigated. These are: 1) Incremental logic resynthesis to control wiring, 2) Coupling wiring with logic restructuring and finding optimizations to eliminate wiring overflows. 3) Use of generalized Reed-Muller forms to analyze logic as an aid to: - designing cell libraries and for technology mapping, - developing new multi level optimization techniques, - designing networks of provably good testability. 4) Develop new methods for power optimization, at the technology independent and technology dependent levels in logic synthesis, and also find better routing tools to handle power constraints.
所提出的研究是布局驱动的综合,即逻辑综合和物理设计的交叉。重点是在综合数字系统中重构逻辑网络。四个主题,这符合提高路由效率或功耗的目标,正在调查。这些是:1)增量逻辑再合成以控制布线,2)将布线与逻辑重构耦合并找到优化以消除布线溢出。3)使用广义Reed-Muller形式来分析逻辑,以帮助:-设计单元库和技术映射,-开发新的多级优化技术,-设计可证明良好可测试性的网络。4)在逻辑综合的技术独立和技术依赖层面上开发新的功耗优化方法,并找到更好的布线工具来处理功耗约束。

项目成果

期刊论文数量(0)
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会议论文数量(0)
专利数量(0)

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Malgorzata Marek-Sadowska其他文献

Theory of wire addition and removal in combinational Boolean networks
  • DOI:
    10.1016/j.mee.2006.02.017
  • 发表时间:
    2007-02-01
  • 期刊:
  • 影响因子:
  • 作者:
    Chih-Wei(Jim) Chang;Malgorzata Marek-Sadowska
  • 通讯作者:
    Malgorzata Marek-Sadowska
Closed-Form Crosstalk Noise Delay Metrics

Malgorzata Marek-Sadowska的其他文献

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{{ truncateString('Malgorzata Marek-Sadowska', 18)}}的其他基金

SHF: Small: Assessing VeSFET Technology for 3-D Integration
SHF:小型:评估用于 3D 集成的 VeSFET 技术
  • 批准号:
    1320401
  • 财政年份:
    2013
  • 资助金额:
    --
  • 项目类别:
    Standard Grant
SHF: Small: Modeling and Preventing Electromigration-Caused Degradation in Cu Dual Damascene Scaled Interconnects
SHF:小型:建模并防止铜双镶嵌互连中电迁移引起的退化
  • 批准号:
    1115663
  • 财政年份:
    2011
  • 资助金额:
    --
  • 项目类别:
    Standard Grant
Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC Designs
合作研究:SGER:基于双栅极晶体管阵列的 IC 设计的布局生成工具
  • 批准号:
    0904124
  • 财政年份:
    2009
  • 资助金额:
    --
  • 项目类别:
    Standard Grant
Interconnect Planning in Placement and Logic Synthesis
布局和逻辑综合中的互连规划
  • 批准号:
    0427821
  • 财政年份:
    2004
  • 资助金额:
    --
  • 项目类别:
    Continuing Grant
Performance Driven Layout and Logic Synthesis
性能驱动布局和逻辑综合
  • 批准号:
    0098069
  • 财政年份:
    2001
  • 资助金额:
    --
  • 项目类别:
    Standard Grant
Research on Logic Synthesis and Layout
逻辑综合与布局研究
  • 批准号:
    9811528
  • 财政年份:
    1998
  • 资助金额:
    --
  • 项目类别:
    Continuing grant

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