Research on Layout and Logic Design

本文的研究方向是版图驱动综合，即逻辑综合和物理设计的交叉。重点是重组合成数字系统中的逻辑网络。四个符合提高布线效率或功耗目标的课题正在调查中。它们是：1)增量逻辑重新综合以控制布线，2)将布线与逻辑重构相结合，并找到消除布线溢出的优化方案。3)使用广义Reed-Muller形式来分析逻辑，以帮助：-设计单元库和用于技术映射，-开发新的多水平优化技术，-设计可证明良好的可测试性的网络。4)在逻辑综合中，在技术独立和技术依赖两个层面上开发新的功耗优化方法，并找到更好的布线工具来处理功耗约束。

The proposed research is on layout driven synthesis, i.e. the intersection of logic synthesis and physical design. The focus is on restructuring logic networks in synthesized digital systems. Four topics, which meet the goals of improving routing efficiency or power consumption, are being investigated. These are: 1) Incremental logic resynthesis to control wiring, 2) Coupling wiring with logic restructuring and finding optimizations to eliminate wiring overflows. 3) Use of generalized Reed-Muller forms to analyze logic as an aid to: - designing cell libraries and for technology mapping, - developing new multi level optimization techniques, - designing networks of provably good testability. 4) Develop new methods for power optimization, at the technology independent and technology dependent levels in logic synthesis, and also find better routing tools to handle power constraints.