Research on Logic Synthesis and Layout

本研究是在亚微米技术的互连设计，与发展的逻辑综合方法，将产生高度规则的布局结构，而不会大面积的惩罚的目标。正在探索的研究问题包括：电路结构和其增量可重构性之间的关系;通过一系列增量变化实现给定特性的网络; RC互连中的同时开关和串扰噪声效应;准确、易于计算的串扰幅度和持续时间的界限;串扰对延迟的影响建模;综合中最小化串扰效应的设计优化技术;以及对可以在布线/导线尺寸调整和/或晶体管尺寸调整步骤中纠正的低水平效应进行建模。该项目还在开发一种方法，以根据电路结构确定串扰预算，以及考虑串扰和延迟的晶体管和导线尺寸工具。缓冲区插入和间隔，网络重新排序，和布尔水平的规律性技术也正在研究中。

This research is on interconnect design in submicron technologies, with the goal of developing a logic synthesis methodology which would produce highly regular layout structures without large area penalty. Research issues being explored include: the relationship between circuit structure and its incremental restructurability; achieving a network of given properties through a sequence of incremental changes; simultaneous switching and cross-talk noise effects in RC interconnects; accurate, easy to compute bounds on crosstalk amplitude and duration; modeling the influence of crosstalk on delay; design optimization techniques for minimizing crosstalk effects in synthesis; and modeling of low-level effects which can be corrected at the routing/wire sizing and/or transistor sizing steps. The project is also developing a methodology to determine crosstalk budgets based on circuit structure, as well as transistor and wire sizing tools which will consider both crosstalk and delay. Techniques for buffer insertion and spacing, net reordering, and Boolean level regularity are also being investigated.